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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13501-6E
16-bit Proprietary Microcontroller
CMOS
F2MC-16F MB90210 Series
MB90214/P214A/P214B/W214A/W214B/V210
s OUTLINE
The MB90210 series is a line of 16-bit microcontrollers particularly suitable for system control of video cameras, VTRs, and copiers. The F2MC-16F CPU integrated in this series is based on the F2MC*-16, while providing enhanced instructions for high-level languages and supporting extended addressing modes. The MB90210 series incorporates a variety of peripheral resources such as a PWC timer with 4 channels, a 10bit A/D converter with 8 channels, UART serial ports with 3 channels (1 channel for CTS and 1 channel for dual input/output pin switching), 16-bit reload timers with 8 channels, and an 8-bit PPG timer with 1 channel. MB90P214B/W214B is under development. *: F2MC stands for FUJITSU Flexible Microcontroller.
s PACKAGE
80-pin Plastic QFP
80-pin Ceramic QFP
(FPT-80P-M06)
(FPT-80C-C02)
MB90210 Series
s FEATURES
F2MC-16F CPU * Minimum execution time: 62.5 ns/16-MHz oscillation (using a duty control system) * Instruction sets optimized for controllers Upward object-compatible with the F2MC-16(H) Various data types (bit, byte, word, and long-word) Instruction cycle improved to speed up operation Extended addressing modes: 25 types High coding efficiency Access method (bank access with linear pointer) Enhanced multiplication and division instructions (with signed instructions added) Higher-precision operation using a 32-bit accumulator * Extended intelligent I/O service (Automatic transfer function independent of instructions) access area expanded to 64 Kbytes * Enhanced instruction set applicable to high-level language (C) and multitasking System stack pointer Enhanced pointer-indirect instructions Barrel shift instruction Stack check function * Increased execution speed: 8-byte instruction queue * Powerful interrupt functions: 8 levels and 29 sources Integrated Peripheral Resources * ROM : 64 Kbytes (MB90214) EPROM : 64 Kbytes (MB90W214A/W214B) OTPROM: 64Kbytes (MB90P214A/P214B) * RAM: 3 Kbytes (MB90214) 4 Kbytes (MB90P214A/P214B/W214A/W214B/V210) * General-purpose ports: max. 65 channels * PWC timer with time measurement function: 4 channels * 10-bit A/D converter: 8 channels * UART: 3 channels * Including: 1 channel with CTS function 1 channel with I/O pin switching function * 16-bit reload timer Toggled output, external clock, and gate functions: 4 channels External clock and gate functions: 4 channels * 8-bit PPG timer: 1 channel * DTP/External-interrupt inputs: 4 channels * Write-inhibit RAM: 256 bytes (MB90V210: 512 bytes) * Timebase counter: 18 bits * Clock gear function * Low-power consumption mode Sleep mode Stop mode Hardware standby mode
2
MB90210 Series
Product Description * MB90214 is a mask ROM product. * MB90P214A/P214B are OTPROM products. * MB90W214A/W214B are EPROM products. ES only. * Operating temperature of MB90P214A/W214A is -40C to +85C. (However, the AC characteristics is assured in -40C to +70C) * MB90V210 is a evaluation device for the program development. ES only.
3
MB90210 Series
s PRODUCT LINEUP
Part number Item Classification ROM size RAM size CPU functions Mask ROM product 64 Kbytes 3 Kbytes MB90214 MB90P214A MB90P214B OTPROM product 64 Kbytes 4 Kbytes MB90W214A MB90W214B EPROM product 64 Kbytes 4 Kbytes 412 8 or 16 bits 1 to 7 bytes 1, 4, 8, 16, or 32 bits 62.5 ns/16 MHz 1.0 s/16 MHz (min.) 8 57 65 MB90V210 For evaluation -- 4 Kbytes
The number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: I/O ports (N-ch open-drain): I/O ports (CMOS): Total:
Ports
PWC timer
Number of channels: 4 16-bit reload timer operation (operating clock cycle: 0.25 s to 1.31 ms) 16-bit pulse-width count operation (Allowing continuous/one-shot measurement, H/L width measurement, inter-edge measurement, and divided-frequency measurement) Resolution: 10 or 8 bits, Number of inputs: 8 Single conversion mode (conversion for each input channel) Scan conversion mode (continuous conversion for up to 8 consecutive channels) Continuous conversion mode (repeated conversion for a selected channel) Stop conversion mode (conversion every fixed cycle) Number of channels: 3 (1 channel with CTS function; 1 channel with I/O pin switching function) Clock-synchronous transfer mode (full-duplex double buffering, 7- to 9-bit data length, 2400 to 62500 bps) Asynchronous transfer mode (full-duplex double buffering, 7- to 9-bit data length, 2400 to 62500 bps) Number of channels: 4 channels x 2 types 16-bit reload timer operation (operating clock cycle: 0.25 s to 1.05 s) Number of channels: 1 8-bit PPG operation (operating clock cycle: 0.25 s to 6 s) Number of inputs: 4 External interrupt mode (allowing interrupts to activate at four different request levels) Simple DMA start mode (allowing extended I2OS to activate at two different request levels) RAM size: 256 bytes (MB90V210: 512 bytes) RAM write-protectable with WI pin Stop mode (activated by software or hardware) and sleep mode Machine clock operating frequency switching: 16, 8, 4, or 1 MHz (at 16 MHz oscillation) FPT-80P-M06 FPT-80C-C02 PGA-256C-A02
10-bit A/D converter
UART
Timer 8-bit PPG timer DTP/External interrupt Write-inhibit RAM Standby mode Gear function Package
4
MB90210 Series
s DIFFERENCES BETWEEN MB90214 (MASK ROM PRODUCT) AND MB90P214A/P214B/ W214A/W214B
Part number MB90214 Item ROM Pin function 43 pins Mask ROM 64 Kbytes MD2 pin MB90P214A MB90P214B OTPROM 64 Kbytes MD2/VPP pin MB90W214A MB90W214B EPROM 64 Kbytes
Note: MB90V210, device used for evaluation, is not warranted for electrical specifications.
5
6
MB90210 Series
s PIN ASSIGNMENT
X1 VCC P00/D00 P01/D01 P02/D02 P03/D03 P04/D04 P05/D05 P06/D06 P07/D07 P10/D08 P11/D09 P12/D10 P13/D11 P14/D12 P15/D13 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
(FPT-80P-M06) (FPT-80C-C02)
(Top view)
P16D14 P17D15 P20A00/TIN0 P21/A01/TIN1 P22/A02/TIN2 P23/A03/TIN3 P24/A04/TIN4 P25/A05/TIN5 P26/A06/TIN6 P27/A07/TIN7 VSS P30/A08 P31/A09/PPG P32/A10/TOUT0 P33/A11/TOUT1 P34/A12/TOUT2 P35/A13/TOUT3 P36/A14/SCK3 P37/A15/S I D3 P40/A16/SOD3 P41/A17/SCK2 P42/A18/S I D2 P43/A19/SOD2 P44/A20/PWC0/POUT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 VSS P61/AN1 P60/AN0 AVSS AVRL AVRH AVCC PWC3/P47/A23/POUT3 PWC2/P46/A22/POUT2 PWC1/P45/A21/POUT1
X0 VSS RST P57/WI P56/RD P55/WRL P54/WRH/CTS0/INT3 P53/HRQ P52/HAK P51/RDY P50/CLK P82/INT2/ATG P81/INT1 P80/INT0 P75/SOD0 P74/SID0 P73/SCK0 P72/SOD1 P71/SID1 P70/SCK1 HST MD2 MD1 MD0
MB90210 Series
s PIN DESCRIPTION
Pin no. QFP* 64, 65 62 66 11, 34, 63 67 to 74 X0, X1 RST VCC VSS Pin name Circuit type A H
Power supply Power supply
Function Crystal oscillator pins (16 MHz) External reset request input pin Digital circuit power supply pin Digital circuit grounding level
P00 to P07 D00 to D07
B
General-purpose I/O ports These ports are available only in the single-chip mode. I/O pins for the lower eight bits of external data bus These pins are available in an external-bus mode.
75 to 80, 1, 2
P10 to P15, P16, P17 D08 to D13, D14, D15
B
General-purpose I/O ports These ports are available in the single-chip mode and in an external-bus mode with the 8-bit data bus specified. I/O pins for the upper eight bits of external data bus These pins are available in an external-bus mode with the 16-bit data bus specified.
3 to 6
P20 to P23 A00 to A03 TIN0 to TIN3
E
General-purpose I/O ports These ports are available only in the single-chip mode. Output pins for external address buses A00 to A03 These pins are available in an external-bus mode. 16-bit reload timer 1 (ch.0 to ch.3) input pins These pins are available when the 16-bit reload timer 1 (ch.0 to ch.3) input specification is "enabled". The data on the pin is read as the 16-bit reload timer 1 (ch.0 to ch.3) input (TIN0 to TIN3).
7 to 10
P24 to P27 A04 to A07 TIN4 to TIN7
E
General-purpose I/O ports These ports are available only in the single-chip mode. Output pins for external address buses A04 to A07 These pins are available in an external-bus mode. 16-bit reload timer 2 (ch.4 to ch.7) input pins These pins are available when the 16-bit reload timer 2 (ch.4 to ch.7) input specification is "enabled". The data on the pin is read as the 16-bit reload timer 2 (ch.4 to ch.7) input (TIN4 to TIN7).
12
P30
E
General-purpose I/O port This port is available in the single-chip mode or when the middle address control register setting is "port." Output pin for external address bus A08 This pin is available in an external-bus mode and when the middle address control register set to "address."
A08
* : FPT-80P-M06, FPT-80C-C02
(Continued)
7
MB90210 Series
Pin no. QFP* 13
Pin name P31
Circuit type E
Function General-purpose I/O port This port is available in the single-chip mode or when the middle address control register setting is "port", with the 8-bit PPG output is disabled. Output pin for external address bus A09 This pin is available in an external-bus mode and when the middle address control register setting is "address." PPG timer output pin This pin is available when the PPG operation mode control register specification is the PPG output pin.
A09
PPG
14 to 17
P32 to P35
E
General-purpose I/O ports These ports are available in the single-chip mode or when the middle address control register setting is "port", with the 16-bit reload timer 1 (ch.0 to ch.3) output is disabled. Output pins for external address buses A10 to A13 These pins are available in an external-bus mode and when the middle address control register setting is "address." 16-bit reload timer 1 (ch.0 to ch.3) output pin These pins are available when the 16-bit reload timer 1 (ch.0 to ch.3) is output operation.
A10 to A13
TOUT0 to TOUT3
18
P36
E
General-purpose I/O port This port is available when the UART (ch.2) clock output is disabled either in the single-chip mode or when the middle address control register setting is "port." Output pin for external address bus A14 This pin is available when the UART (ch.2) clock output is disabled in an external-bus mode and when the middle address control register setting is "address." UART (ch.2) clock output pin (SCK3) This pin is available when the UART (ch.2) clock output is enabled. UART (ch.2) external clock input pin (SCK3) This pin is available when the port is in input mode and the UART (ch.2) specification is external clock mode.
A14
SCK3
19
P37
E
General-purpose I/O port This port is available in the single-chip mode or when the middle address control register setting is "port." Output pin for external address bus A15 This pin is available in an external-bus mode and when middle address control register setting is "address." UART (ch.2) serial data input pin (SID3) Since this input is used whenever the SID3 is in input operation, the output by any other function must be suspended unless the output is intentionally performed.
A15
SID3
* : FPT-80P-M06, FPT-80C-C02
(Continued)
8
MB90210 Series
Pin no. QFP* 20
Pin name P40
Circuit type E
Function General-purpose I/O port This port is available when the UART (ch.2) serial data output from SOD3 is disabled either in the single-chip mode or when the upper address control register setting is "port." Output pin for external address bus A16 This pin is available when the UART (ch.2) serial data output from SOD3 is disabled in an external-bus mode and when the upper address control register setting is "address." UART (ch.2) serial data output pin (SOD3) This pin is available when the UART (ch.2) serial data output is enabled.
A16
SOD3
21
P41
E
General-purpose I/O port This port is available when the UART (ch.2) clock output is disabled either in the single-chip mode or when the upper address control register setting is "port." Output pin for external address bus A17 This pin is available when the UART (ch.2) clock output is disabled in an external-bus mode and when the upper address control register setting is "address." UART (ch.2) clock output pin (SCK2) This pin is available when the UART (ch.2) clock output is enabled. UART (ch.2) external clock input pin (SCK2) This pin is available when the port is in input mode and the UART (ch.2) specification is external clock mode.
A17
SCK2
22
P42
E
General-purpose I/O port This port is available in the single-chip mode or when the upper address control register setting is "port." Output pin for external address bus A18 This pin is available in an external-bus mode and when the upper address control register setting is "address." UART (ch.2) serial data input pin (SID2) Since this input is used whenever the SID2 is in input operation, the output by any other function must be suspended unless the output is intentionally performed.
A18
SID2
23
P43
E
General-purpose I/O port This port is available when the UART (ch.2) serial data output from SOD2 is disabled either in the single-chip mode or when the upper address control register setting is "port." Output pin for external address bus A19 This pin is available when the UART (ch.2) serial data output from SOD2 is disabled in an external-bus mode and when the upper address control register setting is "address." UART (ch.2) serial data output pin (SOD2) This pin is available when the UART (ch.2) serial data output from SOD2 is enabled.
A19
SOD2
* : FPT-80P-M06, FPT-80C-C02
(Continued)
9
MB90210 Series
Pin no. QFP* 24
Pin name PWC0
Circuit type E
Function PWC timer input pin Since this input is used whenever the PWC0 timer is in input operation, the output by any other function must be suspended unless the output is intentionally performed. PWC timer output pin This pin is available when the PWC0 is output operation.
POUT0 25 P45 E
General-purpose I/O port This port is available in the single-chip mode or when the upper address control register setting is "port." Output pin for external address bus A21 This pin is available in an external-bus mode and when the upper address control register setting is "address." PWC timer data sample input pin Since this input is used whenever the PWC1 timer is in input operation, the output by any other function must be suspended unless the output is intentionally performed. PWC timer output pin This pin is available when the PWC1 is output operation.
A21
PWC1
POUT1 26 P46 E
General-purpose I/O port This port is available in the single-chip mode or when the upper address control register setting is "port." Output pin for external address bus A22 This pin is available in an external-bus mode and when the upper address control register setting is "address." PWC timer input pin Since this input is used whenever the PWC2 timer is in input operation, the output by any other function must be suspended unless the output is intentionally performed. PWC timer output pin This pin is available when the PWC2 is output operation.
A22
PWC2
POUT2 27 P47 E
General-purpose I/O port This port is available in the single-chip mode or when the upper address control register setting is "port." Output pin for external address bus A23 This pin is available in an external-bus mode and when the upper address control register setting is "address." PWC timer input pin Since this input is used whenever the PWC3 timer is in input operation, the output by any other function must be suspended unless the output is intentionally performed. PWC timer output pin This pin is available when the PWC3 is output operation.
A23
PWC3
POUT3 * : FPT-80P-M06, FPT-80C-C02
(Continued)
10
MB90210 Series
Pin no. QFP* 54
Pin name P50
Circuit type E
Function General-purpose I/O port This port is available in the single-chip mode and when the CLK output is disabled. CLK output pin This pin is available in an external-bus mode with the CLK output enabled.
CLK
55
P51
E
General-purpose I/O port This port is available in the single-chip mode or when the ready function is disable. Ready signal input pin This pin is available in an external-bus mode and when the ready function is enabled.
RDY
56
P52
E
General-purpose I/O port This port is available in the single-chip mode or when the hold function is disabled. Hold acknowledge output pin This pin is available in an external-bus mode and when the hold function is enabled.
HAK
57
P53
E
General-purpose I/O port This port is available in the single-chip mode or when the hold function is disabled in an external-bus mode. Hold request input pin This pin is available in an external-bus mode and when the hold function is enabled. Since this input is used during this operation at any time, the output by any other function must be suspended unless the output is intentionally performed.
HRQ
58
P54
D
General-purpose I/O port This port is available in the single-chip mode, in the external bus 8-bit mode, or when the WRH pin output is disabled. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS level to use these pins in input mode. UART (ch.0) clear-to-send input pin Since this input is used whenever the UART (ch.0) CTS function is enabled, the output by any other function must be suspended unless the output is intentionally performed. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS level to use these pins in input mode. Write strobe output pin for the upper eight bits of data bus This pin is available in the external bus 16-bit mode with the WRH pin output enabled in an external-bus mode.
CTS0
WRH
* : FPT-80P-M06, FPT-80C-C02
(Continued)
11
MB90210 Series
Pin no. QFP* 58
Pin name INT3
Circuit type D
Function External interrupt request input pin Since this input is used whenever external interrupts are enabled, the output by any other function must be suspended unless the output is intentionally performed. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS level to use these pins in input mode. General-purpose I/O port This port is available in the single-chip mode or when the WRL pin output is disabled. Write strobe output pin for the lower eight bits of data bus This pin is available in an external-bus mode and when the WRL pin output is enabled.
59
P55
E
WRL
60
P56 RD
E
General-purpose I/O port This port is available in the single-chip mode. Data bus read strobe output pin This pin is available in an external-bus mode.
61
P57
D
General-purpose I/O port This port is always available. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS level to use these pins in input mode. RAM write disable request input Since this input is used during this operation at any time, the output by any other function must be suspended unless the output is intentionally performed. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS level to use these pins in input mode.
WI
32, 33, 35 to 40
P60, P61, P62 to P67 AN0, AN1, AN2 to AN7
C
Open-drain I/O ports These ports are available when the analog input enable register setting is "port." 10-bit A/D converter analog input pins These pins are available when the analog input enable register setting is "analog input."
41 to 43 44 45
MD0 to MD2 HST P70
F G E
Operation mode select signal input pins Connect these pins directly to VCC or VSS. Hardware standby input pin General-purpose I/O port This port is available when the UART (ch.1) clock output is disabled.
* : FPT-80P-M06, FPT-80C-C02
(Continued)
12
MB90210 Series
Pin no. QFP* 45
Pin name SCK1
Circuit type E
Function UART (ch.1) clock output pin This pin is available when the UART (ch.1) clock output is enabled. UART (ch.1) external clock input pin This pin is available when the port is in input mode and the UART (ch.1) specification is external clock mode. General-purpose I/O port This port is always available. UART (ch.1) serial data input pin Since this input is used whenever the UART (ch.1) is in input operation, the output by any other function must be suspended unless the output is intentionally performed.
46
P71 SID1
E
47
P72
E
General-purpose I/O port This port is available when the UART (ch.1) serial data output is disabled. UART (ch.1) serial data output pin This pin is available when the UART (ch.1) serial data output is enabled.
SOD1
48
P73
E
General-purpose I/O port This port is available when the UART (ch.0) clock output is disabled. UART (ch.0) clock output pin This pin is available when the UART (ch.0) clock output is enabled. UART (ch.0) external clock input pin This pin is available when the port is in input mode and the UART (ch.0) specification is external clock mode.
SCK0
49
P74 SID0
E
General-purpose I/O port This port is always available. UART (ch.0) serial data input pin Since this input is used whenever the UART (ch.0) is in input operation, the output by any other function must be suspended unless the output is intentionally performed.
50
P75
E
General-purpose I/O port This port is available when the UART (ch.0) serial data output is disabled. UART (ch.0) serial data output pin This pin is available when the UART (ch.0) serial data output is enabled.
SOD0
51, 52
P80, P81
D
General-purpose I/O port This port is always available. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS level to use these pins in input mode.
* : FPT-80P-M06, FPT-80C-C02
(Continued)
13
MB90210 Series
(Continued)
Pin no. QFP* 51, 52 Pin name INT0, INT1 Circuit type D Function External interrupt request input pin Since this input is used whenever external interrupts are enabled, the output by any other function must be suspended unless the output is intentionally performed. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS level to use these pins in input mode. General-purpose I/O port This port is always available. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS level to use these pins in input mode. External interrupt request input pin Since this input is used whenever external interrupts are enabled, the output by any other function must be suspended unless the output is intentionally performed. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS level to use these pins in input mode. 10-bit A/D converter trigger input pin When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS level to use these pins in input mode.
Power supply
53
P82
D
INT2
ATG
28
AVCC
Analog circuit power supply pin This power supply must be turned on or off with a potential equal to or higher than AVCC applied to VCC. Be sure that AVCC= VCC before use and during operation. Analog circuit reference voltage input pin This pins must be turned on or off with a potential equal to or higher than AVRH applied to AVCC. Analog circuit reference voltage input pin Analog circuit grounding level
29
AVRH
Power supply
30 31
AVRL AVSS
Power supply Power supply
* : FPT-80P-M06, FPT-80C-C02
14
MB90210 Series
s I/O CIRCUIT TYPE
Type A
X1
Circuit
Remarks * Oscillation feedback resistor: Approx.1 M MB90214 MB90P214B MB90W214B
X0
Standby control X1
* Oscillation feedback resistor: Approx.1 M MB90P214A MB90W214A
X0
Standby control
B
R Digital output
R R
Digital output
Digital input Standby control
* CMOS-level I/O Standby control provided MB90214: With or without pull-up/pull-down reisistor optional MB90P214A/P214B: Without pull-up/pull-down resistor MB90W214A/W214B: Without pull-up/pull-down resistor
C
* N-ch open-drain output * CMOS-level hysteresis input A/D control provided
R Digital output A/D input Digital input
D
R Digital output
R R
Digital output
Digital input
* CMOS-level output * CMOS-level hysteresis input Standby control not provided MB90214: With or without pull-up/pull-down reisistor optional MB90P214A/P214B: Without pull-up/pull-down resistor MB90W214A/W214B: Without pull-up/pull-down resistor
(Continued)
15
MB90210 Series
(Continued)
Type E
R Digital output
Circuit
Remarks * CMOS-level output * CMOS-level hysteresis input Standby control provided MB90214: With or without pull-up/pull-down reisistor optional MB90P214A/P214B: Without pull-up/pull-down resistor MB90W214A/W214B: Without pull-up/pull-down resistor * CMOS-level input with no standby control Mask ROM products only: MD2: With pull-down resistor MD1: With pull-up resistor MD0: With pull-down resistor
Digital input
R R
Digital output
Digital input
F
R
R
* COMS-level input with no standby control MD2 of OTPROM products/EPROM products only
Digital input VPP power supply
G
* CMOS-level hysteresis input Standby control not provided * With input analog filter (40 ns Typ.)
R
Analog filter
Digital input
H
Pull-up resistor R
R Analog filter Digital input
* CMOS-level hysteresis input Standby control not provided * With input analog filter (40 ns Typ.) * With pull-up resistor MB90214: With or without pull-up/pull-down resistor optional MB90P214A/W214A/P214B/W214B: With pull-up resistor
: P-type transistor
: N-type transistor
Note: The pull-up and pull-down resistors are always connected, regardless of the state. 16
MB90210 Series
s HANDLING DEVICES
1. Preventing Latchup
CMOS ICs may cause latchup when a voltage higher than VCC or lower than VSS is applied to input or output pins, or when a voltage exceeding the rating is applied between VCC and VSS. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let any voltage exceed the maximum rating. Also, take care to prevent the analog power supply (AVCC and AVRH) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor.
3. Treatment of Pins when A/D is not Used
Connect to be AVCC = AVRH = VCC and AVSS = AVRL = VSS even if the A/D converter is not in use.
4. Precautions when Using an External Clock
To reset the internal circuit properly by the Low-level input to the RST pin, the "L" level input to the RST pin must be maintained for at least five machine cycles. Pay attention to it if the chip uses external clock input.
5. VCC and VSS Pins
Apply equal potential to the VCC and VSS pins.
6. Supply Voltage Variation
The operation assurance range for the VCC supply voltage is as given in the ratings. However, sudden changes in the supply voltage can cause misoperation, even if the voltage remains within the rated range. Therefore, it is important to supply a stable voltage to the IC. The recommended power supply control guidelines are that the commercial frequency (50 to 60 Hz) ripple variation (P-P value) on VCC should be less than 10% of the standard VCC value and that the transient rate of change during sudden changes, such as during power supply switching, should be less than 0.1 V/ms.
7. Notes on Using an External Clock
When using an external clock, drive the X0 pin as illustrated below. When an external clock is used, oscillation stabilization time is required even for power-on reset and wake-up from stop mode. * Use of External Clock
X0 MB90210
X1
Note: When using an external clock, be sure to input external clock more than 6 machine cycles after setting the HST pin to "L" to transfer to the hardware standby mode.
17
MB90210 Series
8. Power-on Sequence for A/D Converter Power Supplies and Analog Inputs
Be sure to turn on the digital power supply (VCC) before applying voltage to the A/D converter power supplies (AVCC, AVRH, and AVRL) and analog inputs (AN0 to AN7). When turning power supplies off, turn off the A/D converter power supplies (AVCC, AVRH, and AVRL) and analog inputs (AN0 to AN7) first, then the digital power supply (VCC). When turning AVRH on or off, be careful not to let it exceed AVCC.
18
MB90210 Series
s PROGRAMMING FOR MB90P214A/P214B/W214A/W214B
In EPROM mode, the MB90P214A/P214B/W214A/W214B functions equivalent to the MBM27C1000. This allows the EPROM to be programmed with a general-purpose EPROM programmer by using the dedicated socket adapter (do not use the electronic signature mode).
1. Program Mode
When shipped from Fujitsu, and after each erasure, all bits (64 K x 8 bits) in the MB90P214A/P214B/W214A/ W214B are in the "1" state. Data is written to the ROM by selectively programming "0's" into the desired bit locations. Bits cannot be set to "1" electrically.
2. Programming Procedure
(1) Set the EPROM programmer to MBM27C1000. (2) Load program data into the EPROM programmer at 10000H to 1FFFFH. Note that ROM addresses FF0000H to FFFFFFH in the operation mode in the MB90P214A/P214B/W214A/ W214B series assign to 10000H to 1FFFFH in the EPROM mode (on the EPROM programmer).
FFFFFFH
1FFFFH*
FF0000H Operation mode
10000H* EPROM mode (Corresponding addresses on the EPROM mode)
* : Be sure to set the programming, the start address and the stop address on the EPROM programmer to 10000H/1FFFFH.
(3) Mount the MB90P214A/P214B/W214A/W214B on the adapter socket, then fit the adapter socket onto the EPROM programmer. When mounting the device and the adapter socket, pay attention to their mounting orientations. (4) Start programming the program data to the device. (5) If programming has not successfully resulted, connect a capacitor of approx. 0.1 F between VCC and GND, between VPP and GND. (6) Since the MB90P214A and MB90W214A have CMOS-level input, programming to them may be impossible depending on the output level of the general-purpose programmer. In that case, connect a pull-up resistor to the adapter socket side. Note: The mask ROM products (MB90214) does not support EPROM mode. Data cannot, therefore, be read by the EPROM programmer.
19
MB90210 Series
3. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer
Part No. Package Compatible socket adapter Sun Hayato Co., Ltd. Recommended programmer manufacturer and programmer name R4945A (main unit) + R49451A (adapter) MB90P214B QFP-80 ROM-80QF-32DP-16F
Advantest corp.
Recommended
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX: (81)-3-5396-9106 Advantest Corp.: TEL: Except JAPAN (81)-3-3930-4111
4. Erase Procedure
Data written in the MB90W214A/W214B are erased (from "0" to "1") by exposing the chip to ultraviolet rays with a wavelength of 2,537 A through the translucent cover. Recommended irradiation dosage for exposure is 10 Wsec/cm2. This amount is reached in 15 to 20 minutes with a commercial ultraviolet lamp positioned 2 to 3 cm above the package (when the package surface illuminance is 1200 W/cm2). If the ultraviolet lamp has a filter, remove the filter before exposure. Attaching a mirrored plate to the lamp increases the illuminance by a factor of 1.4 to 1.8, thus shortening the required erasure time. If the translucent part of the package is stained with oil or adhesive, transmission of ultraviolet rays is degraded, resulting in a longer erasure time. In that case, clean the translucent part using alcohol (or other solvent not affecting the package). The above recommended dosage is a value which takes the guard band into consideration and is a multiple of the time in which all bits can be evaluated to have been erased. Observe the recommended dosage for erasure; the purpose of the guard band is to ensure erasure in all temperature and supply voltage ranges. In addition, check the life span of the lamp and control the illuminance appropriately. Data in the MB90W214A/W214B are erased by exposure to light with a wavelength of 4000 A or less. Data in the device is also erased even by exposure to fluorescent lamp light or sunlight although the exposure results in a much lower erasure rate than exposure to 2537 A ultraviolet rays. Note that exposure to such lights for an extended period will therefore affect system reliability. If the chip is used where it is exposed to any light with a wavelength of 4000 A or less, cover the translucent part, for example, with a protective seal to prevent the chip from being exposed to the light. Exposure to light with a wavelength of 4,000 to 5,000 A or more will not erase data in the device. If the light applied to the chip has a very high illuminance, however, the device may cause malfunction in the circuit for reasons of general semiconductor characteristics. Although the circuit will recover normal operation when exposure is stopped, the device requires proper countermeasures for use in a place exposed continuously to such light even though the wavelength is 4,000 A or more.
20
MB90210 Series
5. Recommended Screening Conditions
High temperature aging is recommended as the pre-assembly screening procedure.
Program, verify
Aging +150C, 48 Hrs.
Data verification
Assembly
6. Programming Yeild
MB90P214A/P214B cannot be write-tested for all bits due to their nature. Therefore the write yield cannot always be guaranteed to be 100%.
7. Pin Assignment in EPROM Mode
(1) Pins compatible with MBM27C1000 MBM27C1000 Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin name VPP OE A15 A12 A07 A06 A05 A04 A03 A02 A01 A00 D00 D01 D02 GND
MB90P214A, MB90P214B, MB90W214A, MB90W214B
MBM27C1000 Pin no. 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Pin name VCC PGM N.C. A14 A13 A08 A09 A11 A16 A10 CE D07 D06 D05 D04 D03
MB90P214A, MB90P214B, MB90W214A, MB90W214B
Pin no. 43 59 19 16 10 9 8 7 6 5 4 3 67 68 69
Pin name MD2 (VPP) P55 P37 P34 P27 P26 P25 P24 P23 P22 P21 P20 P00 P01 P02
Pin no. 60 18 17 12 13 15 20 14 58 74 73 72 71 70
Pin name P56 P36 P35 P30 P31 P33 P40 P32 P54 P07 P06 P05 P04 P03
21
MB90210 Series
(2) Power supply and ground connection pins Type Power supply Pin no. 41 42 44 66 11 30 31 34 56 57 62 63 MD0 MD1 HST VCC VSS AVRL AVSS VSS P52 P53 RST VSS Pin name
GND
(3) Pins other than MBM27C1000-compatible pins Pin no. 64 65 1 2 21 to 27 28 29 32 33 35 to 40 45 to 50 51 to 53 54 55 61 75 to 80 X0 X1 P16 P17 P41 to P47 AVCC AVRH P60 P61 P62 to P67 P70 to P75 P80 to P82 P50 P51 P57 P10 to P15 Pin name Pull up to 4.7 k. Open Treatment
Connect a pull-up resistor of approximately 1 M to each pin.
22
MB90210 Series
s BLOCK DIAGRAM
4 X1 X0 RST HST MD2 MD1 MD0 WI PWC0 to PWC3 /POUT0 to POUT3
7
Clock controller
PWC timer x4 Internal data bus
Write-inhibit RAM
4 INT0 to INT3 DTP/External interrupt x4 D00 to D15 A00 to A23 CLK RDY HAK HRQ WRH WRL RD
CTS0 SCK3 SID3 SOD3 SCK2 SID2 SOD2 SCK1 SID1 SOD1 SCK0 SID0 SOD0 TOUT0 to TOUT3 TIN0 to TIN3
13 UART x 3 External bus interface 47
8
16-bit timer 1 x4
F2MC-16F CPU
RAM TIN4 to TIN7 4 16-bit timer 2 x4 ROM 13 10-bit A/D converter 8 ch.
ATG AN0 to AN7 AVCC AVRH AVRL AVSS P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P75 P80 to P82
65
8-bit I/O port PPG timer
PPG
8-bit PPG timer
23
MB90210 Series
s PROGRAMMING MODEL
Dedicated Registers
AH AL USP SSP PS PC USPCU SSPCU USPCL SSPCL DPR PCB DTB USB SSB ADB 8 bits 16 bits 32 bits Accumulator
User stack pointer System stack pointer Processor status Program counter User stack upper register System stack upper register User stack lower register System stack lower register Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register
General-purpose Registers
Upper
Max.32 banks
R7 R5 R3 R1 RW3
R6 R4 R2 R0
RW 7 RL 3 RW 6 RW 5 RL 2 RW 4 RL 1
Lower
RW 2 RW 1 RL 0
000180H + RP x 10H
RW 0 16 bits
Processor Status (PS)
ILM RP
MSB --
LSB
I
S
T
N
Z
V
C
CCR
24
MB90210 Series
s MEMORY MAP
Single chip FFFFFFH Internal ROM and external bus External ROM and external bus
ROM area
ROM area
Address #1
010000H ROM area FF bank image Address #2 Address #3 Address #4 Write-inhibit RAM Address #5 Write-inhibit RAM Write-inhibit RAM ROM area FF bank image
Address #6 : Internal 000380H RAM 000180H 000100H 0000C0H Peripherals 000000H Peripherals Peripherals : No access : External Registers RAM Registers RAM Registers
Type MB90214 MB90P214A/P214B MB90W214A/W214B MB90V210
Address #1
Address #2
Address #3
Address #4
Address #5
Address #6
FF0000H FF0000H (FE0000H)
004000H 004000H 004000H
001300H 001300H 001300H
001200H 001200H 001300H
001100H 001100H 001100H
000D00H 001100H 001100H
25
MB90210 Series
s I/O MAP
Address Register Register name PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 11111111 - - XXXXXX --- -- XX X
000000H *3 Port 0 data register 000001H *3 Port 1 data register 000002H *3 Port 2 data register 000003H *
3
Port 3 data register
000004H *3 Port 4 data register 000005H *3 Port 5 data register 000006H 000007H 000008H 000009H to 0FH 000010H *3 Port 0 data direction register 000011H *
3
Port 6 data register Port 7 data register Port 8 data register
(Reserved area) *1 DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 ADER DDR7 DDR8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 00000000 00000000 00000000 00000000 00000000 00000000 11111111 - - 0 00 00 0 - - - - - 0 00
Port1 data direction register
000012H *3 Port 2 data direction register 000013H *3 Port 3 data direction register 000014H *
3
Port 4 data direction register
000015H *3 Port 5 data direction register 000016H 000017H 000018H 000019H to 1FH 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H Mode control register 0 Status register 0 Input data register 0/output data register 0 Rate and data register 0 Mode control register 1 Status register 1 Input data register 1/output data register 1 Rate and data register 1 Analog input enable register Port 7 data direction register Port 8 data direction register
(Reserved area) *1 UMC0 USR0 UIDR0/ UODR0 URD0 UMC1 USR1 UIDR1/ UODR1 URD1 R/W R/W R/W R/W R/W R/W R/W R/W UART (ch.1) UART (ch.0) 00000100 00010000 XXXXXXXX 00000000 00000100 00010000 XXXXXXXX 00000000
(Continued)
26
MB90210 Series
Address 000028H 000029H 00002AH 00002BH 00002CH 00002DH to 2FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H to 37H 000038H to 39H 00003AH to 3BH 00003CH to 3DH 00003EH to 3FH 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H
Register Mode control register 2 Status register 2 Input data register 2/output data register 2 Rate and data register 2 UART redirect control register
Register name UMC2 USR2 UIDR2/ UODR2 URD2 URDR
Access R/W R/W R/W R/W R/W
Resource name UART (ch.2)
Initial value 00000100 00010000 XXXXXXXX 00000000
UART (ch.0/2)
- - - 0 0000
(Reserved area) *1 Interrupt/DTP enable register Interrupt/DTP factor register Request level setting register ENIR EIRR ELVR R/W R/W R/W DTP/external interrupt - - - - 0000 - - - - 0000 00000000
(Reserved area) *1 AD control status register AD data register Timer control status register 0 Timer control status register 1 Timer control status register 2 Timer control status register 3 Timer 0 timer register Timer 0 reload register Timer 1 timer register Timer 1 reload register ADCS ADCD TMCSR0 TMCSR1 TMCSR2 TMCSR3 TMR0 TMRLR0 TMR1 TMRLR1 R/W R/W *4 R/W R/W R/W R/W R W R W 16-bit reload timer 1 (ch.1) 16-bit reload timer 1 (ch.0) 16-bit reload timer 1 (ch.1) 16-bit reload timer 1 (ch.2) 16-bit reload timer 1 (ch.3) 16-bit reload timer 1 (ch.0) 10-bit A/D converter 00000000 00000000 XXXXXXXX 0 - - - - - XX 00000000 - - - - 0 0 00 00000000 - - - - 0 0 00 00000000 - - - - 0 0 00 00000000 - - - - 0 0 00 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
(Continued)
27
MB90210 Series
Address 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH 00005DH 00005EH 00005FH 000060H 000061H 000062H 000063H 000064H 000065H
Register Timer 2 timer register Timer 2 reload register Timer 3 timer register Timer 3 reload register Timer 4 timer register Timer 4 reload register Timer 5 timer register Timer 5 reload register Timer 6 timer register Timer 6 reload register Timer 7 timer register Timer 7 reload register Timer control status register 4
Register name TMR2 TMRLR2 TMR3 TMRLR3 TMR4 TMRLR4 TMR5 TMRLR5 TMR6 TMRLR6 TMR7 TMRLR7 TMCSR4
Access R W R W R W R W R W R W R/W
Resource name 16-bit reload timer 1 (ch.2)
Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
16-bit reload timer 1 (ch.3)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
16-bit reload timer 2 (ch.4)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
16-bit reload timer 2 (ch.5)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
16-bit reload timer 2 (ch.6)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
16-bit reload timer 2 (ch.7)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
16-bit reload timer 2 (ch.4)
00000000
(Reserved area) *1 Timer control status register 5 TMCSR5 R/W 16-bit reload timer 2 (ch.5) 00000000
(Reserved area) *1 Timer control status register 6 TMCSR6 R/W 16-bit reload timer 2 (ch.6) 00000000
(Reserved area) *1
(Continued)
28
MB90210 Series
Address 000066H 000067H 000068H 000069H 00006AH 00006BH 00006CH 00006DH 00006EH 00006FH 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH 000080H to 87H 000088H 000089H
Register Timer control status register 7
Register name TMCSR7
Access R/W
Resource name 16-bit reload timer 2 (ch.7)
Initial value 00000000
(Reserved area) *1 PWC0 divide ratio register DIVR0 R/W PWC timer (ch.0) ------00
(Reserved area) *1 PWC1 divide ratio register DIVR1 R/W PWC timer (ch.1) ------00
(Reserved area) *1 PWC2 divide ratio register DIVR2 R/W PWC timer (ch.2) ------00
(Reserved area) *1 PWC3 divide ratio register DIVR3 R/W PWC timer (ch.3) ------00
(Reserved area) *1 PWC0 control status register PWC0 data buffer register PWC1 control status register PWC1 data buffer register PWC2 control status register PWC2 data buffer register PWC3 control status register PWC3 data buffer register PWCSR0 PWCR0 PWCSR1 PWCR1 PWCSR2 PWCR2 PWCSR3 PWCR3 R/W R/W R/W R/W R/W R/W R/W R/W PWC timer (ch.3) PWC timer (ch.2) PWC timer (ch.1) PWC timer (ch.0) 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (Reserved area) *1 PPG operation mode control register PPGC R/W 8-bit PPG timer 00000--1
(Reserved area) *1
(Continued)
29
MB90210 Series
Address 00008AH 00008BH 00008CH to 8DH 00008EH 00008FH to 9EH 00009FH 0000A0H 0000A1H to A2H 0000A3H 0000A4H 0000A5H 0000A6H to A7H 0000A8H 0000A9H 0000AAH to AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H
Register PPG reload register
Register name PRL
Access R/W
Resource name 8-bit PPG timer
Initial value XXXXXXXX XXXXXXXX
(Reserved area) *1 WI control register WICR R/W
Write-inhibit RAM
-- - X -- - -
(Reserved area) *1 Delayed interrupt source generate/ release register Standby control register DIRR STBYC R/W R/W
Delayed interrupt generation module
-------0 0001
Low-power consumption mode
(Reserved area) *1 Middle address control register Upper address control register External pin control register MACR HACR EPCR W W W External pin ######## ######## ##0-0#00
(Reserved area) *1 Watchdog timer control register Timebase timer control register WTC TBTC R/W R/W Watchdog timer Timebase timer XXXXXXXX 1 - -0 0 00 0
(Reserved area) *1 Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller 0 0 00 0 11 1 0 0 00 0 11 1 0 0 00 0 11 1 0 0 00 0 11 1 0 0 00 0 11 1 0 0 00 0 11 1 0 0 00 0 11 1 0 0 00 0 11 1 0 0 00 0 11 1 0 0 00 0 11 1
(Continued)
30
MB90210 Series
(Continued)
Address 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H to FFH Register Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Register name ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Access R/W R/W R/W R/W R/W R/W Resource name Interrupt controller Initial value 0 0 00 0 11 1 0 0 00 0 11 1 0 0 00 0 11 1 0 0 00 0 11 1 0 0 00 0 11 1 0 0 00 0 11 1
(External area) *2
Initial value 0: The initial value of this bit is 0. 1: The initial value of this bit is 1. X: The initial value of this bit is undefined. -: This bit is not used. The initial value is undefined. : The initial value of this bit varies with the reset source. #: The initial value of this bit varies with the operation mode. *1: Access inhibited *2: The only area available for the external access below address 0000FFH is this area. Accesses to these addresses are handled as accesses to an external I/O area. *3: When the external bus is enabled, do not access any register not serving as a general-purpose port in the areas from address 000000H to 000005H and from 000010H to 000015H. *4: Writing to bit 15 is possible. Writing to other bits is used as a test function.
31
MB90210 Series
s INTERRUPT SOURCES AND INTERRUPT VECTORS/INTERRUPT CONTROL REGISTERS
Interrupt source Reset INT9 instruction Exceptional UART interrupt #0 UART interrupt #1 UART interrupt #2 UART interrupt #3 PWC timer # 0 * count completed PWC timer # 0 * overflow PWC timer # 1 * count completed PWC timer # 1 * overflow PWC timer # 2 * count completed PWC timer # 2 * overflow PWC timer # 3 * count completed PWC timer # 3 * overflow 16-bit reload timer 1 # 0 overflow 16-bit reload timer 1 # 1 overflow 16-bit reload timer 1 # 2 overflow 16-bit reload timer 1 # 3 overflow 16-bit reload timer 2 # 4 overflow 16-bit reload timer 2 # 5 overflow 16-bit reload timer 2 # 6 overflow 16-bit reload timer 2 # 7 overflow A/D converter count completed Timebase timer interval interrupt UART2 * transmission completed UART2 * reception completed EI2OS support x x x Interrupt vector No. # 08 # 09 # 10 # 11 # 12 # 13 # 14 # 15 # 16 # 17 # 18 # 19 # 20 # 21 # 22 # 23 # 24 # 25 # 26 # 27 # 28 # 29 # 30 # 31 # 32 # 33 # 34 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H ICR00 FFFFCCH FFFFC8H ICR01 FFFFC4H FFFFC0H ICR02 FFFFBCH FFFFB8H ICR03 FFFFB4H FFFFB0H ICR04 FFFFACH FFFFA8H ICR05 FFFFA4H FFFFA0H ICR06 FFFF9CH FFFF98H ICR07 FFFF94H FFFF90H ICR08 FFFF8CH FFFF88H ICR09 FFFF84H FFFF80H ICR10 FFFF7CH FFFF78H ICR11 FFFF74H 000BBH 000BAH 000B9H 000B8H 000B7H 000B6H 000B5H 000B4H 000B3H 000B2H 000B1H 000B0H Interrupt control register ICR -- -- -- Address -- -- --
(Continued)
32
MB90210 Series
(Continued)
Interrupt source UART1 * transmission completed UART1 * reception completed UART0 * transmission completed UART0 * reception completed Delayed interrupt generation module Stack fault x x EI2OS support Interrupt vector No. # 35 # 36 # 37 # 39 # 42 # 255 23H 24H 25H 27H 2AH FFH Address FFFF70H ICR12 FFFF6CH FFFF68H FFFF60H FFFF54H FFFC00H ICR13 ICR14 ICR15 -- 0000BDH 0000BEH 0000BFH -- 0000BCH Interrupt control register ICR Address
: EI2OS is supported (with stop request). : EI2OS is supported; however, since two interrupt sources are allocated to a single ICR, in case EI2OS is used for one of the two, EI2OS and ordinary interrupt are not both available for the other (with stop request). : EI2OS is supported; however, since two interrupt sources are allocated to a single ICR, in case EI2OS is used for one of the two, EI2OS and ordinary interrupt are not both available for the other (with no stop request). x : EI2OS is not supported.
33
MB90210 Series
s PERIPHERAL RESOURCES
1. Parallel Ports
The MB90210 series has 57 I/O pins and 8 open-drain I/O pins. Ports 0 to 5, 7, and 8 are I/O ports. Each of these ports serves as an input port when the data direction register value is 0 and as an output port when the value is 1. Port 6 is an open-drain port, which may be used as a port when the analog input enable register value is 0. (1) Register Configuration * Port data registers 0 to 8 (PDR0 to PDR8)
Port data register Address: PDR1 PDR3 PDR5 PDR7 000001 H 000003H 000005H 000007H Bit PDx7 15 PDx6 (R/W) (X) 7 PDx7 PDx6 14 PDx5 (R/W) (X) 6 PDx5 13 PDx4 (R/W) (X) 5 PDx4 12 PDx3 (R/W) (X) 4 PDx3 11 PDx2 (R/W) (X) 3 PDx2 10 PDx1 (R/W) (X) 2 PDx1 9 PDx0 (R/W) (X) 1 PDx0 0 PDRx 8
Read/write (R/W) Initial value (X) Port data register Address: PDR0 PDR2 PDR4 PDR6 PDR8 Bit 000000 H 000002H 000004H 000006H 000008H Read/write Initial value
(R/W) (X) (1)
(R/W) (X) (1)
(R/W) (X) (1)
(R/W) (X) (1)
(R/W) (X) (1)
(R/W) (X) (1)
(R/W) (X) (1)
(R/W) (X) (1) Only for the PDR6
Note: No register bit is included in bits 7 and 6 of port 7 or bits 7 to 3 of port 8.
* Port direction registers 0 to 5, 7, and 8 (DDR0 to DDR5, DDR7, and DDR8)
Port direction register Address: DDR1 DDR3 DDR5 DDR7 Bit DDx7 15 DDx6 (R/W) (0) 7 DDx7 DDx6 14 DDx5 (R/W) (0) 6 DDx5 13 DDx4 (R/W) (0) 5 DDx4 12 DDx3 (R/W) (0) 4 DDx3 11 DDx2 (R/W) (0) 3 DDx2 10 DDx1 (R/W) (0) 2 DDx1 9 DDx0 (R/W) ( 0) 1 DDx0 0 DDRx 8
000011 H 000013H 000015H 000017H
Read/write (R/W) Initial value (0) Port direction register Address: DDR0 DDR2 DDR4 DDR8 Bit 000010 H 000012H 000014H 000018H Read/write Initial value
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
Note: No register bit is included in bits 7 and 6 of port 7 or bits 7 to 3 of port 8. Port 6 has no DDR.
34
MB90210 Series
* Analog input enable register (ADER)
Analog input enable register Address: ADER 000016 H Read/write Initial value Bit 7 ADE7 (R/W) (1) 6 ADE6 (R/W) (1) 5 ADE5 (R/W) (1) 4 ADE4 (R/W) (1) 3 ADE3 (R/W) (1) 2 ADE2 (R/W) (1) 1 ADE1 (R/W) (1) 0 ADE0 (R/W) (1) ADER
(2) Block Diagram * I/O port (Port 0 to 5, 7, and 8)
Port data register read Internal data bus Port data register Port data register write Port direction register Port direction register write Pin
Port direction register read
* I/O port with an open-drain output (Port 6)
RMW (Read-modify-write instruction) Port data register read Internal data bus Port data register Port data register write Analog input enable register Analog input enable register write
Pin
Analog input enable register read
35
MB90210 Series
2. 16-bit Reload Timer 1 (with Event Count Function)
The 16-bit reload timer 1 consists of a 16-bit down counter, a 16-bit reload register, an input pin (TIN), an output pin (TOUT), and a control register. The input clock can be selected from among three internal clocks and one external clock. At the output pin (TOUT), the pulses in the toggled output waveform are output in the reload mode; the rectangular pulses indicating that the timer is counting are in the single-shot mode. The input pin (TIN) can be used for event input in the event count mode, and for trigger input or gate input in the internal clock mode. MB90210 series contains four channels for this timer. (1) Register Configuration * Timer control status register (TMCSR)
Timer control status register (Upper byte) Address: ch.0 ch.1 ch.2 ch.3 000039H 00003BH 00003DH 00003FH Read/write Initial value Timer control status register (Lower byte) Bit Address: ch.0 000038 H ch.1 00003AH ch.2 00003CH ch.3 00003EH Read/write Initial value
Bit -- (--) (--)
15 -- (--) (--) 7 MDO0 (R/W) (0)
14 -- (--) (--) 6
13 -- (--) (--) 5
12 CSL1 (R/W) (0) 4
11 CSL0 (R/W) (0) 3 INTE (R/W) (0)
10 MOD2 (R/W) (0) 2 UF (R/W) (0)
9 MOD1 (R/W) (0) 1 CNTE (R/W) (0)
8
0 TRG (R/W) (0) TMCSRx
OUTE (R/W) (0)
OUTL (R/W) (0)
RELD (R/W) (0)
* Timer register (TMR)
Timer register (Upper byte) Address: ch.0 ch.1 ch.2 ch.3 000041H 000045H 000049H 00004DH Read/write Initial value Timer register (Lower byte) Address: ch.0 ch.1 ch.2 ch.3 Bit 000040H 000044H 000048H 00004CH Read/write Initial value (R) (X) (R) (X) 7 (R) (X) 6 (R) (X) 5 (R) (X) 4 (R) (X) 3 (R) (X) 2 (R) (X) 1 0 TMRx (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X)
Bit
15
14
13
12
11
10
9
8
36
MB90210 Series
* Reload register (TMRLR)
Reload register (Upper byte) Address: ch.0 ch.1 ch.2 ch.3 000043H 000047H 00004BH 00004FH Read/write Initial value Reroal register (Lower byte) Address: ch.0 ch.1 ch.2 ch.3 Bit 000042H 000046H 00004AH 00004EH Read/write Initial value (W) (X) (W) (X) 7 (W) (X) 6 (W) (X) 5 (W) (X) 4 (W) (X) 3 (W) (X) 2 (W) (X) 1 0 TMRLRx (W) (X) (W) (X) (W) (X) (W) (X) (W) (X) (W) (X) (W) (X) (W) (X) Bit 15 14 13 12 11 10 9 8
(2) Block Diagram
16 16-bit reload register 8 Reload RELD 16-bit down counter 16 Internal data bus 2 GATE CSL 1 Clock selector CSL 0 2 IN CTL EXCK 2
1
UF
OUTE OUTL OUT CTL. 2 I NTE UF CNTE TRG Retrigger Port (TIN) IRQ Clear EI2 OSCLR
2
3
2
5
3 Prescaler clear MOD 2 MOD 1
Port (TOUT) UART (timer 1 ch.2 output) A/D (timer 1 ch.3 output)
Internal clock 3
MOD 0
37
MB90210 Series
3. 16-bit Reload Timer 2 (with Gate Mode)
The 16-bit reload timer 2 consists of a 16-bit down counter, a 16-bit reload register, an input pin (TIN), and an 8-bit control register. The input clock can be selected from among four internal clocks. The MB90210 series contains four channels for this timer. (1) Register Configuration * Timer control status register (TMCSR)
Timer control status register Address: ch.4 ch.5 ch.6 ch.7 000060 H 000062H 000064H 000066H Read/write Initial value Bit CSL1 7 CSL0 6 GATE 5 GATL 4 RELD 3 INTE 2 UF 1 STRT 0 TMCSRx
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
* Timer register (TMR)
Timer register (Upper byte) Address: ch.4 ch.5 ch.6 ch.7 000051H 000055H 000059H 00005DH Read/write Initial value Timer register (Lower byte) Address: ch.4 ch.5 ch.6 ch.7 000050H 000054H 000058H 00005CH Read/write Initial value (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) Bit (R) (X) (R) (X) 7 (R) (X) 6 (R) (X) 5 (R) (X) 4 (R) (X) 3 (R) (X) 2 (R) (X) 1 0 TMRx Bit 15 14 13 12 11 10 9 8
* Reload register (TMRLR)
Reload register (Upper byte) Address: ch.4 ch.5 ch.6 ch.7 000053H 000057H 00005BH 00005FH Read/write Initial value Reload register (Lower byte) Address: ch.4 ch.5 ch.6 ch.7 000052H 000056H 00005AH 00005EH Read/write Initial value (W) (X) (W) (X) (W) (X) (W) (X) (W) (X) (W) (X) (W) (X) (W) (X) Bit (W) (X) (W) (X) 7 (W) (X) 6 (W) (X) 5 (W) (X) 4 (W) (X) 3 (W) (X) 2 (W) (X) 1 0 TMRLRx Bit 15 14 13 12 11 10 9 8
38
MB90210 Series
(2) Block Diagram
16 16-bit reload register 4 Reload
16 Internal data bus
16-bit down counter 2 GATE
UF RELD INTE UF STRT IRQ
CSL 1 Clock selector CSL 0 2 IN CTL 22 25 26 28 2 GATE GATL
Clear EI 2 OSCLR Clear (RELD = 0)
Port (TIN)
2
39
MB90210 Series
4. UART
The UART is a serial I/O port for synchronous or asynchronous communication with external resources. It has the following features: * * * * * * * * * * Full duplex double buffer Data transfer synchronous or asynchronous with clock pulses Multiprocessor mode support (Mode 2) Built-in dedicated baud-rate generator (Nine types) Arbitrary baud-rate setting from external clock input or internal timer (Use the 16-bit reroad timer 1 channel 2 for internal timer.) Variable data length (7 to 9 bits (without parity bit); 6 to 8 bits (with parity bit)) Variable data length (7 to 9 bit no parity, 6 to 8 bit with parity) Error detection function (Framing, overrun, parity) Interrupt function (Two sources for transmission and reception) Transfer in NRZ format The MB90210 series contains three channels for the UART. UART channel 0 has the CTS function. UART channel 2 provides dual I/O pin switching. (1) Register Configuration * Serial mode control register (UMC)
Serial mode control register Address: ch.0 ch.1 ch.2 000020 H 000024H 000028H Read/write Initial value Bit PEN (R/W) (0) 7 SBL (R/W) (0) 6 MC1 (R/W) (0) 5 MC0 (R/W) (0) 4 SMDE (R/W) (0) 3 RFC (W) (1) 2 SCKE (R/W) (0) 1 SOE (R/W) (0) 0 UMC
* Status register (USR)
Status register Address: ch.0 ch.1 ch.2 000021 H 000025H 000029H Read/write Initial value Bit RDRF (R) (0) 15 ORFE (R) (0) 14 PE (R) (0) 13 TDRE (R) (1) 12 RIE (R/W) (0) 11 TIE (R/W) (0) 10 RBF (R) (0) 9 TBF (R) (0) 8
USR
* Input data register (UIDR)/output data register (UODR)
Input data register/output data register Address: ch.0 ch.1 ch.2 000022 H 000026H 00002AH Read/write Initial value Bit D7 (R/W) (X) 7 D6 (R/W) (X) 6 D5 (R/W) (X) 5 D4 (R/W) (X) 4 D3 (R/W) (X) 3 D2 (R/W) (X) 2 D1 (R/W) (X) 1 D0 (R/W) (X) 0 UIDR (read)/ UODR (write)
40
MB90210 Series
* Rate and data register (URD)
Rate and data register Address: ch.0 ch.1 ch.2 000023 H 000027H 00002BH Bit BCH 15 RC3 (R/W) (0) 14 RC2 (R/W) (0) 13 RC1 (R/W) (0) 12 RC0 (R/W) (0) 11 BCH0 (R/W) (0) 10 P (R/W) (0) 9 D8 (R/W) (0) 8
URDx
Read/write (R/W) Initial value (0)
* UART redirect control register (URDR)
UART redirect control register Bit Address: 00002C H Read/write Initial value 7 -- (--) (--) 6 -- (--) (--) 5 -- (--) (--) 4 CTE (R/W) (0) 3 CSP (R/W) (0) 2 CTSE (R/W) (0) 1 UDPE (R/W) (0) 0 SEL3 (R/W) (0) URDR
41
MB90210 Series
(2) Block Diagram
CONTROL BUS Reception interrupt (To CPU) Dedicated baud-rate clock 16-bit reload timer 1 channel 2 (internally connected) External clock Reception control circuit Transmission control circuit Transmitting clock pulse Clock selector circuit Receiving clock pulse SCK0 to SCK3 Transmission interrupt (To CPU)
SID0 to SID3
Start bit detector
Transmission control circuit Transmission bit counter Transmission parity counter
Received bit counter
Recieved parity bit counter
SOD0 to SOD3
Reception status detection circuit
Reception shifter
Transmission shifter
End of reception SIDR Reception error occurence signal for EI2OS (To CPU) Internal data bus
Start of transmission UODR
UMC register
PEN SBL MC1 MC0 SMDE RFC SCKE SOE
USR register
RDRF ORFE PE TDRE RIE TIE RBF TBF
URD register
BCH RC3 RC2 RC1 RC0 BCH0 P D8
CONTROL BUS
42
MB90210 Series
5. 10-bit A/D Converter
The 10-bit A/D converter converts the analog input voltage to a digital value. It has the following features: Conversion time: min.6.125 s per channel (at 16-MHz machine clock) RC-type successive approximation with built-in sample-and-hold circuit 10-bit or 8-bit resolution Eight analog input channels programmable for selection Single conversion mode: Selects and converts one channel. Scan conversion mode: Converts multiple consecutive channels (up to eight channels programmable). Consecutive conversion mode: Converts a specified channel repeatedly. Stop conversion mode: Converts one channel and suspends its own operation until the next activation (allowing synchronized conversion start). * On completion of A/D conversion, the converter can generate an interrupt request to the CPU. This interrupt generation can activate the EI2OS to transfer the A/D conversion result to memory, making the converter suitable for continuous operation. * Conversion can be activated by software, external trigger (falling edge), and/or timer (rising edge) as selected. Use the 16-bit reroad timer 1 channel 3 for the timer. * * * * (1) Register Configuration * A/D Control status register (ADCS1 and ADCS0)
A/D Control status register (Upper byte) Address: 000035 H Bit 15 BUSY 14 INT (R/W) (0) 6 MD0 (R/W) (0) 13 INTE (R/W) (0) 5 ANS2 (R/W) (0) 12 PAUS (R/W) (0) 4 ANS1 (R/W) (0) 11 STS1 (R/W) (0) 3 ANS0 (R/W) (0) 10 STS0 (R/W) (0) 2 ANE2 (R/W) (0) 9 STRT (W) (0) 1 ANE1 (R/W) (0) 8 -- (--) (0) 0 ANE0 (R/W) (0) ADCS0 ADCS1
Read/write (R/W) Initial value (0) A/D Control status register (Lower byte) Address: 000034 H Read/write Initial value Bit 7 MD1
(R/W) (0)
* A/D Data registers (ADCD1 and ADCD0)
A/D Data register (Upper byte) Address: 000037 H Read/write Initial value A/D Data register (Lower byte) Address: 000036 H Read/write Initial value Bit Bit 15 S10 (W) (0) 7 D7 14 -- (--) (--) 6 D6 (R) (X) 13 -- (--) (--) 5 D5 (R) (X) 12 -- (--) (--) 4 D4 (R) (X) 11 -- (--) (--) 3 D3 (R) (X) 10 -- (--) (--) 2 D2 (R) (X) 9 D9 (R) (X) 1 D1 (R) (X) 8 D8 (R) (X) 0 D0 (R) (X) ADCD0 ADCD1
(R) (X)
43
MB90210 Series
(2) Block Diagram
AV CC AVRH/AVRL AV SS
D/A converter MPX AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Input circuit
Successive approximation register Internal data bus A/D data register ADCD0, ADCD1 ADCS0, ADCS1 Operation clock Prescaler
Comparator
Sample-and-hold circuit
Decorder Trigger activation ATG Timer activation 16-bit reload timer 1 channel 3 (internally connected) Machine clock ()
A/D control status register
44
MB90210 Series
6. PWC(Pulse Width Count) Timer
The PWC (pulse width count) timer is a 16-bit multifunction up-count timer with an input-signal pulse-width count function and a reload timer function. The hardware configuration of this module is a 16-bit up-count timer, an input pulse divider with divide ratio control register, four count input pins, and a 16-bit control register. Using these components, the PWC timer provides the following features: * Timer functions: An interrupt request can be generated at set time intervals. Pulse signals synchronized with the timer cycle can be output. The reference internal clock can be selected from among three internal clocks. * Pulse-width count functions: The time between arbitrary pulse input events can be counted. The reference internal clock can be selected from among three internal clocks. Various count modes: "H" pulse width ( to ) /"L" pulse width ( to ) Rising-edge cycle ( to ) /Falling-edge cycle ( to ) Count between edges ( or to or ) Cycle count can be performed by 22n division (n = 1, 2, 3, 4) of the input pulse, with an 8 bit input divider. An interrupt request can be generated once counting has been performed. The number of times counting is to be performed (once or subsequently) can be selected. The MB90210 series contains four channels for the PWC timer. (1) Register Configuration * PWC control status register (PWCSR)
PWC control status register (Upper byte) Address: ch.0 000071 H ch.1 000075H ch.2 000079H ch.3 00007DH Bit STRT 15 STOP (R/W) (0) 7 CKS1 (R/W) (0) CKS0 (R/W) (0) 14 EDIR (R) (0) 6 PIS1 (R/W) (0) 13 EDIE (R/W) (0) 5 PIS0 (R/W) (0) 12 OVIR (R/W) (0) 4 S/C (R/W) (0) 11 OVIE (R/W) (0) 3 MOD2 (R/W) (0) 10 ERR (R) (0) 2 MOD1 (R/W) (0) 9 POUT (R/W) (0) 1 MOD0 (R/W) (0) 0 PWCSRx 8
Read/write (R/W) Initial value (0) PWC control status register (Lower byte) Address: ch.0 ch.1 ch.2 ch.3 000070 H 000074H 000078H 00007CH Read/write Initial value Bit
45
MB90210 Series
* PWC data buffer register (PWCR)
PWC data buffer register (Upper byte) Address: ch.0 000073 H ch.1 000077H ch.2 00007BH ch.3 00007FH Bit 15 14 13 12 11 10 9 8
Read/write (R/W) Initial value (0) PWC data buffer register (Lower byte) Address: ch.0 ch.1 ch.2 ch.3 000072 H 000076H 00007AH 00007EH Read/write Initial value (R/W) (0) Bit
(R/W) (0) 7
(R/W) (0) 6
(R/W) (0) 5
(R/W) (0) 4
(R/W) (0) 3
(R/W) (0) 2
(R/W) (0) 1 0 PWCR
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
* PWC divide ratio control register (DIVR)
Divide ratio control register Address: ch.0 ch.1 ch.2 ch.3 000068 H 00006AH 00006CH 00006EH Read/write Initial value Bit -- (--) (--) 7 -- (--) (--) 6 -- (--) (--) 5 -- (--) (--) 4 -- (--) (--) 3 -- (--) (--) 2 DIV1 (R/W) (0) 1 DIV0 (R/W) (0) 0 DIVR
46
MB90210 Series
(2) Block Diagram
PWCR read Error detection 16 PWCR 16 16 Write enable Reload Data transfer Overflow 16 Clock 22 2 Timer clear Control circuit Flag setting, etc.
Control bit output
3
ERR
Internal clock (machine clock/4)
Internal data bus
16-bit up-count timer
Clock divider
Count enable
CKS 1 CKS 0 Divider clear PWC0 PWC1 PWC2 PWC3
Start edge select
Count start edge
End edge Dividing select ON/OFF
Count edge end
Edge detection PIS 1 CKS 1 ERR PIS 0 CKS 0 Divide ratio select 2 DIVR 8-bit divider PIS 1 PIS 0
Count end interrupt edge
Overflow interrupt request
15 PWCSR Overflow F.F. POUT *
* : The POUT pins of the MB90210 series are assigned as follows: Channel PWC PWC PWC PWC ch.0 ch.1 ch.2 ch.3 POUT pin P44/A20/PWC0/POUT0 P45/A21/PWC1/POUT1 P46/A22/PWC2/POUT2 P47/A23/PWC3/POUT3
47
MB90210 Series
7. 8-bit PPG Timer
This block is an 8-bit reload timer module for PPG output by controlling pulse output according to the timer operation. The hardware configuration of this block is an 8-bit down counter, two 8-bit reload registers, an 8-bit control register, and an external pulse output pin. Using these components, the module provides the following features: PPG output operation: The module outputs pulse waves of any period and duty factor. It can also be used as a D/A converter using an external circuit. (1) Register Configuration * PPG operation mode control register (PPGC)
PPG operation mode control register Address: 000088 H Read/write Initial value Bit 7 PEN (R/W) (0) 6 PCKS (R/W) (0) 5 POE (R/W) (0) 4 Reserved (R/W) (0) 3 PUF (R/W) (0) 2 -- (--) (--) 1 -- (--) (--) 0 Reserved (R/W) (1) PPGC
* PPG reload registers (PRLL and RRLH)
PPG reload register Address: 00008B H Read/write (R/W) Initial value (X)
Bit 15
14
13
12
11
10
9
8 PRLH
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
PPG reload register Address: 00008A H
Bit
7
6
5
4
3
2
1
0 PRLL
Read/write Initial value
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
48
MB90210 Series
(2) Block Diagram
PPG output pin
(Port section) Output enable Output A of timebase counter Output B of timebase counter PPG output latch Invert Clear
PEN
Count clock selection
PCNT (Down counter) Reload L/H selector
PRLL
PRLBH
PRLH Low-byte data bus High-byte data bus PPGC Operation mode control
49
MB90210 Series
8. DTP/External Interrupt
The data transfer peripheral (DTP) is located between external peripherals and the F2MC-16F CPU. It receives a DMA request or an interrupt request generated by the external peripherals and reports it to the F2MC-16F CPU to activate the extended intelligent I/O service or interrupt handler. The user can select two request levels of "H" and "L" for extended intelligent I/O service or, and four request levels of "H," "L," rising edge and falling edge for external interrupt requests. (1) Register Configuration
* Interrupt/DTP enable register (ENIR)
Interrupt/DTP enable register Address: 000030H Read/write Initial value Bit 7 -- (--) (--) 6 -- (--) (--) 5 -- (--) (--) 4 -- (--) (--) 3 EN3 (R/W) (0) 2 EN2 (R/W) (0) 1 EN1 (R/W) (0) 0 EN0 (R/W) (0) ENIR
* Interrupt/DTP source register (EIRR)
Interrupt/DTP source register Address: 000031 H Read/write Initial value Bit 15 -- (--) (--) 14 -- (--) (--) 13 -- (--) (--) 12 -- (--) (--) 11 ER3 (R/W) (0) 10 ER2 (R/W) (0) 9 ER1 (R/W) (0) 8 ER0 (R/W) (0) EIRR
* Request level setting register (ELVR)
Request level setting register Address: 000032 H Read/write Initial value Bit 7 LB3 (R/W) (0) 6 LA3 (R/W) (0) 5 LB2 (R/W) (0) 4 LA2 (R/W) (0) 3 LB1 (R/W) (0) 2 LA1 (R/W) (0) 1 LB0 (R/W) (0) 0 LA0 (R/W) (0) ELVR
50
MB90210 Series
(2) Block Diagram
4 Internal data bus
Interrupt/DTP enable register 4
4 4
Gate
Source F/F
Edge detection circuit
INT
Interrupt/DTP source register
8
Request level setting register
51
MB90210 Series
9. Watchdog Timer and Timebase Timer
The watchdog timer consists of a 2-bit watchdog counter using carry signals from an 18-bit timebase timer as the clock source, a control register, and a watchdog reset control section. The timebase timer consists of an 18bit timer and an interval interrupt control circuit. (1) Register Configuration * Watchdog timer control register (WTC)
Watchdog timer control register Address: 0000A8H Read/write Initial value Bit 7 PONR 6 STBR (R) (X) 5 WRST (R) (X) 4 ERST (R) (X) 3 SRST (R) (X) 2 WTE (W) (X) 1 WT1 (W) (X) 0 WT0 (W) (X) WTC
(R) (X)
* Timebase timer control register (TBTC)
Timebase timer control register Address: 0000A9H Read/write Initial value Bit 15 Reserved (W) (1) 14 -- (--) (--) 13 -- (--) (--) 12 TBIE (R/W) (0) 11 TBOF (R/W) (0) 10 TBR (R) (0) 9 TBC1 (R/W) (0) 8 TBC0 (R/W) (0) TBTC
52
MB90210 Series
(2) Block Diagram
Oscillation clock TBTC TBC1 TBC0 TBR TBIE AND TBOF Timebase interrupt WTC WT1 Selector WT0 WTE PONR STBR WRST ERST SRST RST pin From RST bit in STBYC register 2-bit counter OF CLR Watchdog reset generator CLR WDGRST To internal reset generator Q S R 2 12 2 14 2 16 2 18 TBTRES Clock input Timebase timer 2 14 2 16 2 17 2 18
Selector
Internal data bus
From power-on occurence From hardware standby control circuit
53
MB90210 Series
10. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate an interrupt for task switching. Using this module allows an interrupt request to the F2MC-16F CPU to generate or cancel by software. (1) Register Configuration * Delayed interrupt source generate/release register (DIRR)
Delayed interrupt source generate/release register Bit 15 Address: 00009FH Read/write Initial value -- (--) (--) 14 -- (--) (--) 13 -- (--) (--) 12 -- (--) (--) 11 -- (--) (--) 10 -- (--) (--) 9 -- (--) (--) 8 R0 (R/W) (0) DIRR
(2) Block Diagram
Internal data bus
Delayed interrupt source generate/release register
Source latch
54
MB90210 Series
11. Write-inhibit RAM
The write-inhibit RAM is write-protectable with the WI pin input. Maintaining the "L" level input to the WI pin prevents a certain area of RAM from being written. The WI pin has a 4-machine-cycle filter. (1) Register Configuration * WI control register (WICR)
WI control register Address: 00008EH Read/write Initial value Bit 7 -- 6 -- (--) (--) 5 -- (--) (--) 4 WI (R/W) (1) 3 -- (--) (--) 2 -- (--) (--) 1 -- (--) (--) 0 -- (--) (--) WICR
(--) (--)
(2) Write-inhibit RAM Area Write-inhibit RAM area 001100H to 0011FFH (MB90214/P214A/P214B/W214A/W214B) 001100H to 0012FFH (MB90V210) (3) Block Diagram
Access to other area 4-machine-cycle skew removal 4-machine-cycle skew removal S R Q S Q
Write-inhibit circuit Select RAM decoder
WR
WI
L H
Preceded
Writeinhibit RAM
R
Internal data bus
55
MB90210 Series
12. Low-power Consumption Modes, Oscillation Stabilization Delay Time, and Gear Function
The MB90210 series has three low-power consumption modes: the sleep mode, the stop mode, the hardware standby mode, and gear function. Sleep mode is used to suspend only the CPU operation clock; the other components remain in operation. Stop mode and hardware standby mode stop oscillation, minimizing the power consumption while holding data. The clock gear function divides the external clock frequency, which is used usually as it is, to provide a lower machine clock frequency. This function can therefore lower the overall operation speed without changing the oscillation frequency. The function can select the machine clock as a division of the frequency of crystal oscillation or external clock input by 1, 2, 4, or 16. The OSC1 and OSC0 bits can be used to set the oscillation stabilization delay time for wake-up from stop mode or hardware standby mode. (1) Register Configuration * Standby control register (STBYC)
Standby control register Address: 0000A0H Read/write Initial value Bit 7 STP 6 SLP (W) (0) 5 SPL (R/W) (0) 4 RST (R/W) (1) 3 OSC1 (R/W) (*) 2 OSC0 (R/W) (*) 1 CLK1 (R/W) (*) 0 CLK0 (R/W) (*) STBYC
(W) (0)
Note: The initial value(*) of bit0 to bit3 is changed by reset source.
56
MB90210 Series
(2) Block Diagram
Oscillation clock Gear divider circuit 1/1 1/2 1/4 1/16 STBYC CLK1 Selector CLK0 Peripheral clock generator Standby control circuit STP RST Clear HST start HST pin Interrupt request or RST OSC1 Selector OSC0 20 16 2 17 2 18 2 Clock input Timebase timer 2
14
CPU clock generator
CPU clock
Peripheral clock
Internal data bus
SLP
2
16
2
17
2
18
SPL
Pin high-impedance control circuit
Pin HI-Z
RST pin RST Internal reset generator Internal RST To watchdog timer WDGRST
57
MB90210 Series
s ELECTRICAL CHARACTERISTICS (MB90V210, device used for evaluation, is excluded)
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V) Parameter Power supply voltage Program voltage Symbol VCC VPP AVCC Analog power supply voltage AVRH AVRL VI *1 VO IOL IOL IOH IOH Pd TA Tstg Pin name VCC VPP AVCC AVRH AVRL -- *2 *3 *3 *2 *2 -- -- -- Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -- -- -- -- -- -40 -40 -55 Max. VSS + 7.0 13.0 VCC + 0.3 AVCC VCC + 0.3 VCC + 0.3 20 50 -10 -48 650 +105 +85 +150 Unit V V V V V V mA mA mA mA mW C C C MB90214/P214B/W214B MB90P214A/W214A Rush current Total output current Rush current Total output current MB90P214A/W214A MB90P214B/W214B Power supply voltage for A/D converter Reference voltage for A/D converter Remarks
Input voltage Output voltage "L" level output current "L" level total output current "H" level output current "H" level total output current Power consumption Operating temperature Storage temperature
*1: VI and VO must not exceed VCC + 0.3 V. *2: Output pins P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P75, P80 to P82 *3: Output pins P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P75, P80 to P82 WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
58
MB90210 Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V) Parameter Symbol Pin name Value Min. 4.5 Power supply voltage VCC VCC 3.0 4.5 AVRL AVSS 10 -40 Operating temperature TA* -- -40 -40 * : Excluding the temperature rise due to the heat produced. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. Max. 5.5 5.5 VCC + 0.3 AVCC AVRH 16 +105 +85 +70 Unit V V V V V MHz C C C Single-chip mode MB90214/P214B/W214B Single-chip mode MB90P214A/W214A External bus mode Remarks When operating Retains the RAM state in stop mode Power supply voltage for A/D converter Reference voltage for A/D converter
AVCC Analog power supply voltage Clock frequency AVRH AVRL FC
AVCC AVRH AVRL --
59
MB90210 Series
3. DC Characteristics
Single-chip mode MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +105C) MB90P214A/W214A : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) External bus mode : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +70C) Parameter Symbol VIH "H" level input voltage VIHS VIHM VIL "L" level input voltage VILS VILM "H" level output voltage VOH VOH1 VOL VOL1 Pin name *1 *2
MD0 to MD2
Condition -- -- -- -- -- -- VCC = 4.5 V IOH = -4.0 mA VCC = 4.5 V IOH = -2.0 mA VCC = 4.5 V IOL = 4.0 mA VCC = 4.5 V IOL = 2.0 mA VCC =5.5 V
0.2 VCC < VI < 0.8 VCC
Value Min. 0.7 VCC 0.8 VCC
VCC - 0.3 VSS- 0.3 VSS - 0.3 VSS - 0.3 VCC - 0.5
Typ. -- -- -- -- -- -- -- -- -- --
Max.
VCC + 0.3 VCC + 0.3 VCC + 0.3
Unit V V V V V V V V V V
Remarks CMOS level input Hysteresis input CMOS level input Hysteresis input
*1 *2
MD0 to MD2
0.3 VCC 0.2 VCC
VSS+ 0.3
*3 X1 *4 X1 *1 *2 X0
VCC VCC 0.4
VCC - 2.3
VCC - 2.3
"L" level output voltage
0 0
Input leakage current
II
--
--
10
A
Except pins with pull-up/pull-down resistor and RST pin
II2 Analog power supply voltage IA IAH
VCC =5.5 V
0.2 VCC < VIH < 0.8 VCC
-- -- -- --
-- 3 -- 10
25 7 5*5 --
A mA A pF *7 MB90214 MB90P214A/ W214A/P214B/ W214B *7 MB90214 *7 MB90214 *7 MB90214 *7 MB90214 In stop mode, TA = +25C
FC = 16 MHz AVCC *6 -- --
Input capacitance CIN
RST Pull-up resistor RpuIU MD1 Generic pin MD0, MD2 Pull-down resistor RpuID Generic pin
--
22
50
110
k
-- -- -- --
110 22 110 22
300 50 300 50
650 110 650 110
k k k k
(Continued)
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MB90210 Series
(Continued)
Parameter Symbol Pin name Condition Value Min. -- ICC Power supply voltage*9 VCC FC = 16 MHz -- -- Typ. 50*8 70*8 -- Max. 80 100 40 Unit Remarks
mA MB90214 MB90P214A/ W214A mA MB90P214B/ W214B mA In sleep mode TA = +25C In stop mode In hardware standby input time
ICCS
VCC
FC = 16 MHz
ICCH
VCC
--
--
5
10
A
*1: CMOS level input (P00 to P07, P10 to P17, X0) *2: Hysteresis input pins (RST, HST, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67 P70 to P75, P80 to P82) *3: Output pins (P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P75, P80 to P82) *4: Output pins (P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P75, P80 to P82) *5: The current value applies to the CPU stop mode with A/D converter inactive (VCC = AVCC = AVRH = +5.5 V). *6: Other than VCC, VSS, AVCC and AVSS *7: A list of availabilities of pull-up/pull-down resistors Pin name RST MD1 MD0, MD2 Generic pin MB90214 Availability of pull-up resistors is optionally defined. Pull-up resistors available Pull-down resistors available Availability of pull-up/pull-down resistors is optionally defined. MB90P214A/W214A Pull-up resistors available Unavailable Unavailable Unavailable MB90P214B/W214B Pull-up resistors available Unavailable Unavailable Unavailable
*8: VCC = +5.0 V, VSS = 0.0 V, TA = +25C, FC = 16 MHz *9: Measurement condition of power supply current; external clock pin and output pin are open. Measurement condition of VCC; see the table above mentioned.
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MB90210 Series
2. AC Characteristics
(1) Clock Timing Standards Single-chip mode MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +105C) MB90P214A/W214A : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) External bus mode : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +70C) Value Pin Symbol name Condition Unit Remarks Parameter Min. Typ. Max. Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time FC tC PWH PWL tcr tcf X0, X1 X0, X1 X0 X0 -- -- -- -- 10 62.5 0.4 tC -- -- -- -- -- 16 100 0.6 tC 8 MHz ns ns ns 1/FC Duty ratio: 60% tcr + tcf
* Clock Input Timings
tC 0.7 VCC X0 PWH tcf PWL tcr 0.7 VCC 0.3 VCC
* Clock Conditions
When a crystal or ceramic resonator is used
When an external clock is used
X0
X1
X0
X1 Open
C1
C2
C1 = C2 = 10 pF Select the optimum capacity value for the resonator.
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MB90210 Series
* Relationship between Clock Frequency and Power Supply Voltage
V CC [V]
Single-chip mode (MB90214/P214B/W214B) (MB90P214A/W214A) External bus mode
: (TA = -40C to +105C, FC = 10 to 16 MHz) : (TA = -40C to +85C, FC = 10 to 16 MHz) : (TA = -40C to +70C, FC = 10 to 16 MHz)
5.5 Operation assurance range 4.5
0
10
16
FC [MHz]
(2) Clock Output Timing Standards External mode: (VCC = +4.5 to +5.5 V, VSS = 0.0 V, TA = -40C to +70C) Value Pin Condition Unit Remarks name Min. Typ. Max. CLK Load condition: 80 pF 62.5 tCYC/ 2 - 20 -- -- 1600 tCYC/2 ns ns *
Parameter Machine cycle time CLK CLK
Symbol tCYC tCHCL
* : tCYC = n/FC, n gear ratio (1, 2, 4, 16)
tCYC tCHCL
CLK
1/2 VCC
1/2 VCC
63
MB90210 Series
(3) Recommended Resonator Manufacturers * Sample Application of Piezoelectric Resonator (FAR Series)
X0
X1
FAR
*1
C1 *2
C2 *2 *1: Fujitsu Acoustic Resonator
FAR part number Frequency (built-in capacitor type) FAR-C4C F-1 6000- 02 FAR-C4C F-1 6000- 12 Inquiry: FUJITSU LIMITED
Initial deviation of FAR frequency (TA = +25C) 0.5% 0.5%
Temperature characteristics of FAR frequency (TA = -20C to +60C) 0.5% 0.5%
Load capacitance*2
16.00
Built-in
(4) Reset and Hardware Standby Input Standards Single-chip mode MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +105C) MB90P214A/W214A : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) External bus mode : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +70C) Value Pin Symbol Condition Unit Remarks Parameter name Min. Typ. Max. Reset input time tRSTL RST HST Hardware standby input time tHSTL -- 5 tCYC 5 tCYC -- -- -- -- ns ns *
* : The machine cycle (tCYC) at hardware standby input is set to 1/16 divided oscillation.
tRSTL, tHSTL
RST HST
0.2 VCC 0.2 VCC
64
MB90210 Series
(5) Power on Supply Specifications (Power-on Reset) Single-chip mode MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +105C) MB90P214A/W214A : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) External bus mode : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +70C) Value Pin Symbol Condition Unit Remarks Parameter name Min. Typ. Max. Power supply rising time Power supply cut-off time tR tOFF VCC VCC -- -- -- 1 -- -- 30 -- ms ms *
* : Before the power rising, VCC must be less than +0.2 V. Notes: * The above specifications are for the power-on reset. * Always apply power-on reset using these specifications, regardless of whether or not the power-on reset is needed. * There are some internal registers (such as STBYC) which are only initialized by the power-on reset. * Power-on Reset
tR
VCC
4.5 V 0.2 V 0.2 V tOFF 0.2 V
Note: Caution on switching power supply Abrupt change of supply voltage may initiate power-on reset, even if the above requirements are not met. It is, therefore, recommended to power up gradually during the instantaneous change of power supply as shown in the figure below. * Changing Power Supply
Main power supply voltage The rising edge should be 50 mV/ms or less. Subpower supply voltage
VSS
65
MB90210 Series
(6) Bus Read Timing (VCC = +4.5 to +5.5 , VSS = 0.0 V, TA = -40C to +70C) Value Condition Unit Remarks Min. Max. tCYC/2 - 20 tCYC - 25 -- D15 to D00 Load condition: 80 pF A23 to A00 A23 to A00 CLK RD, CLK 0 -- tCYC/2 - 20 tCYC/2 - 25 tCYC/2 - 25 -- -- tCYC - 30 -- 3 tCYC/2 - 40 -- -- -- ns ns ns ns ns ns ns ns
Parameter Valid address RD time RD pulse width RD valid data input RD data hold time Valid address valid data input RD address valid time Valid address CLK time RD CLK time
Symbol tAVRL tRLRH tRLDV tRHDX tAVDV tRHAX tAVCH tRLCL
Pin name A23 to A00 RD
tAVCH
tRLCL 0.7 VCC 0.3 VCC
CLK
tAVRL
tRLRH 0.3 VCC 0.7 VCC
RD
tRHAX
A23 to A00
0.7 VCC 0.3 VCC tRLDV tAVDV tRHDX
0.7 VCC 0.3 VCC
D15 to D00
0.7 VCC 0.3 VCC
Read data
0.7 VCC 0.3 VCC
66
MB90210 Series
(7) Bus Write Timing (VCC = +4.5 to +5.5 V, VSS = 0.0 V, TA = -40C to +70C) Value Condition Unit Remarks Min. Max. tCYC/2 - 20 tCYC - 25 Load condition: 80 pF tCYC - 40 tCYC/2 - 20 tCYC/2 - 20 tCYC/2 - 25 -- -- -- -- -- -- ns ns ns ns ns ns
Parameter
Symbol
Pin name A23 to A00 WRL, WRH D15 to D00 A23 to A00 WRL, WRH, CLK
Valid address WR time tAVWL WR pulse width Valid data output WR time WR data hold time WR CLK time tWLWH tDVWH tWHDX tWLCH
WR address valid time tWHAX
tWLCL 0.3 VCC
CLK
tWLWH
WR (WRL, WRH)
tAVWL
0.3 VCC
0.7 VCC
tWHAX 0.7 VCC 0.3 VCC
A23 to A00
tDVWH
tWHDX 0.7 VCC
D15 to D00
Undefined
Write data 0.3 VCC
67
MB90210 Series
(8) Ready Signal Input Timing (VCC = +4.5 to +5.5 V, VSS = 0.0 V, TA = -40C to +70C) Value Condition Unit Remarks Min. Max. Load condition: 80 pF 40 0 -- -- ns ns
Parameter RDY setup time RDY hold time
Symbol Pin name tRYHS tRYHH RDY
Note: Use the auto-ready function if the RDY setup time is insufficient.
CLK
0.7 VCC
0.7 VCC
A23 to A00
RD/WR (WRL, WRH)
RDY No wait
tRYHS 0.8 VCC
tRYHH 0.8 VCC
tRYHS
tRYHH
Wait
0.2 VCC
0.8 VCC
0.8 VCC
(9) Hold Timing (VCC = +4.5 to +5.5 V, VSS = 0.0 V, TA = -40C to +70C) Value Condition Unit Remarks Min. Max. Load condition: 80 pF 30 tCYC tCYC 2tCYC ns ns
Parameter Pin floating HAK time HAK pin valid time
Symbol tXHAL tHAHV
Pin name HAK
Note: It takes at least one cycle for HAK to vary after HRQ is fetched.
HRQ
0.8 VCC 0.2 VCC
HAK
tXHAL
0.3 VCC
0.7 VCC tHAHV
Each pin
High impedance
68
MB90210 Series
(10) UART Timing MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +105C) MB90P214A/W214A : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) External bus mode : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +70C) Value Pin Symbol name Condition Unit Remarks Parameter Min. Max. Serial clock cycle time tSCYC SCLK SOUT delay time Valid SIN SCLK SCLK Valid SIN hold time tSLOV tIVSH tSHIX -- Load condition: 80 pF 8 tCYC -80 100 60 4 tCYC 4 tCYC -- 60 60 -- 80 -- -- -- -- 150 -- -- ns ns ns ns ns ns ns ns ns External shift clock mode output pin Internal shift clock mode output pin Single-chip mode
Serial clock "H" pulse tSHSL width Serial clock "L" pulse width SCLK SOUT delay time Valid SIN SCLK SCLK Valid SIN hold time tSLSH tSLOV tIVSH tSHIX
Notes: * These AC characteristics assume the CLK synchronous mode. * tCYC is the machine cycle (unit: ns).
69
MB90210 Series
* Internal Shift Clock Mode
tSCYC
SCK
0.7 VCC 0.3 VCC
tSLOV
0.3 VCC 0.7 VCC 0.3 VCC
tIVSH tSHIX
SOD
SID
0.8 VCC 0.2 VCC
0.8 VCC 0.2 VCC
* External Shift Clock Mode
tSLSH
tSHSL
SCK
0.8 VCC 0.2 VCC
tSLOV
0.2 VCC 0.7 VCC 0.3 VCC
tIVSH tSHIX
0.2 VCC
SOD
SID
0.8 VCC 0.2 VCC
0.8 VCC 0.2 VCC
70
MB90210 Series
(11) Resource Input Timing MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +105C) MB90P214A/W214A : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) External bus mode : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +70C) Value Symbol Pin name Condition Unit Remarks Parameter Min. Typ. Max. 4 tCYC TIN0 to TIN3 2 tCYC Input pulse width tTIWH tTIWL Load condition: PWC0 to PWC3 80 pF TIN4 to TIN7 INT0 to INT3 ATG tWIWL WI 2 tCYC 2 tCYC 3 tCYC 2 tCYC 4 tCYC -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns -- -- ns External event count input mode Trigger input/ Gate input mode Gate input mode Single-chip mode
0.8 VCC TIN0 to TIN7 PWC0 to PWC3 INT0 to INT3 WI
tTIWH
0.8 VCC 0.2 VCC 0.2 VCC
tTIWL, tWIWL
(12) Resource Output Timing MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +105C) MB90P214A/W214A : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) External bus mode : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +70C) Value Symbol Pin name Condition Unit Remarks Parameter Min. Max. Single-chip mode CLK TOUT transition time tTO TOUT0 to TOUT3 PPG POUT0 to POUT3 Load condition: 80 pF -- 30 ns
CLK
0.7 VCC
TOUT0 to TOUT3 PPG POUT0 to POUT3
0.7 VCC 0.3VCC tTO
71
MB90210 Series
5. A/D Converter Electrical Characteristics
Single-chip mode MB90214/P214B/W214B: (AVCC = VCC = +5.010%, AVSS = VSS = 0.0 V, TA = -40C to +105C, +4.5 V AVRH - AVRL) Single-chip mode MBP90214A/W214A: (AVCC = VCC = +5.010%, AVSS = VSS = 0.0 V, TA = -40C to +85C, +4.5 V AVRH - AVRL) External bus mode: (AVCC = VCC = +5.010%, AVSS = VSS = 0.0 V, TA = -40C to +70C, +4.5 V AVRH - AVRL) Value Unit Remarks Symbol Pin name Condition Parameter Min. Typ. Max. Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling period Analog port input current Analog input voltage Analog reference voltage Reference voltage supply current Interchannel disparity n -- -- -- VOT AN0 to AN7 VFST TCONV TSAMP IAIN AN0 to AN7 VAIN -- IR IRH -- AVRH AVRL AVRH AN0 to AN7 -- -- -- -- -- -- AVRL AVRL AVSS -- -- -- -- -- -- 200 -- -- AVRH AVCC AVRH 500 5* 4 V V V A A LSB -- tCYC = 62.5 ns -- -- 3.75 -- -- -- -- 0.1 s A --
AVRH - 3.5 AVRH - 1.5 AVRH + 0.5 LSB
-- -- -- --
-- -- -- -- --
-- -3.0 -2.0 --
-- -- -- --
10 +3.0 +2.0 1.5
bit LSB LSB LSB
AVRL - 1.5 AVRL + 0.5 AVRL + 2.5 LSB
6.125
--
--
s
98 machine
cycles
60 machine
cycles
* : The current value applies to the CPU stop mode with the A/D converter inactive (VCC = AVCC = AVRH = +5.5 V). Notes: (1) The smaller the | AVRH - AVRL |, the greater the error would become relatively. (2) Use the output impedance of the external circuit for analog input under the following conditions: . External circuit output impedance < approx. 10 k (Sampling period = 3.75 s, tCYC = 62.5 ns) . (3) Precision values are standard values applicable to sleep mode. (4) If VCC/AVCC or VSS/AVSS is caused by a noise to drop to below the analog input voltage, the analog input current is likely to increase. In such cases, a bypass capacitor or the like should be provided in the external circuit to suppress the noise.
72
MB90210 Series
* Equivalent Circuit of Analog Input Circuit
Analog input R ON1 RON1: Approx. 1.5 k RON2: Approx. 1.5 k C0: Approx. 60 pF C1: Approx. 4 pF Note: The values shown here are reference values. R ON2 C1 C0 Comparator External impedance
6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter When the number of bits is 10, analog voltage can be divided into 210 = 1024. Total error: Difference between actual and logical values. This error is caused by a zero transition error, full-scale transition error, linearity error, differential linearity error, or by noise. Linearity error: The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1111" "11 1111 1110") from actual conversion characteristics Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value.
Digital output 11 1111 1111 11 1111 1110 11 1111 1101
* * * *
Theoretical value Actual conversion value
Theoretical value V NT Total error
N+1 N N-1
* * * *
Linerity error N x 1LSB + V 0T
00 0000 0010 00 0000 0001 00 0000 0000 AVRL
*
*
*
V NT V(N-1)T V(N+1)T AVRH - AVRL 1LSB = VFST - V0T * 1LSB theoretical value = 1022 1022 N = 0 to 1022 VNT- (N x 1LSB + V0T) Linearity error = VNT (N = 0) = V0T 1LSB VNT (N = 1022) = VFST VNT - V(N - 1) T Differential linearity error = - 1 N = 1 to 1022 1LSB V 0T V 1T V 2T VNT - { ( N + 0.5 ) x 1LSB theoretical value } Total error = N = 0 to 1022 1LSB theoretical value
AVRH (V) V FST
*
73
MB90210 Series
s EXAMPLE CHARACTERISTICS
(1) Power Supply Current
I CC vs. T A example characteristics I CC (mA) 100 90 80 MB90P214A 70 F C = 16 MHz External clock input V CC = 5.5 V
I CCH vs. T A example characteristics I CCH (A) 40 V CC = 5.5 V 30
20
10 60 50 40 -50 0 50 T A (C) 100 150 MB90214 0
-10 -50 0 50 T A (C) 100 150
Note: These are not assured value of characteristics but example characteristics. (2) Output Voltage
V OH vs. I OH example characteristics V OH (V) 5.5 T A = +25C V CC = 5.0 V 5.0
V OL vs. I OL example characteristics V OL (V) 2.0 T A = +25C V CC = 5.0 V 1.5
4.5
1.0
4.0
0.5
3.5
0.0
3.0 -15 -10 -5 I OH (mA) 0 5
-0.5 -5 0 5 10 I OL (mA) 15 20 25
Note: These are not assured value of characteristics but example characteristics.
74
MB90210 Series
(3) Pull-up/Pull-down Resistor
Pull-down resistor example characteristics R pul D (k) 100 90 80 70 60 50 40 30 20 -50 0 50 T A (C) Pull-down resistor example characteristics R pul D (k) 500 V CC = 5.5 V 400 300 200 100 -50 0 50 T A (C) 100 150 400 300 200 100 -50 0 50 T A (C) 100 150 V CC = 5.5 V 100 150 V CC = 4.5 V V CC = 5.0 V V CC = 5.5 V Pull-up resistor example characteristics R pul U (k) 100 90 80 70 60 50 40 30 20 -50 0 50 T A (C) Pull-up resistor example characteristics R pul U (k) 500 100 150 V CC = 4.5 V V CC = 5.0 V V CC = 5.5 V
Note: These are not assured value of characteristics but example characteristics. (4) Analog Filter
Analog filter example characteristics Input pulse width (ns) 80 T A = +25C 70 60 50 40 30 20 10 4.0 4.5 5.0 V CC (V) 5.5 6.0 Filtering enable
Note: These are not assured value of characteristics but example characteristics. 75
MB90210 Series
s INSTRUCTIONS (421 INSTRUCTIONS)
Table 1 Item Mnemonic Description of Items in Instruction List Description English upper case and symbol: Described directly in assembler code. English lower case: Converted in assembler code. Number of letters after English lower case: Describes bit width in code. Describes number of bytes. Describes number of cycles. For other letters in other items, refer to table 4. Describes correction value for calculating number of actual states. Number of actual states is calculated by adding value in the ~section. Describes operation of instructions. Describes a special operation to 15 bits to 08 bits of the accumulator. Z : Transfer 0. X : Sign-extend and transfer. - : No transmission Describes a special operation to the upper 16-bit of the accumulator. * : Transmit from AL to AH. - : No transfer. Z : Transfer 00H to AH. X : Sign-extend AL and transfer 00H or FFH to AH. Describes status of I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry) flags. * : Changes after execution of instruction. - : No changes. S : Set after execution of instruction. R : Reset after execution of instruction.
# ~ B Operation LH
AH
I S T N Z V C RMW
Describes whether or not the instruction is a read-modify-write type (a data is read out from memory etc. in single cycle, and the result is written into memory etc.). * : Read-modify-write instruction - : Not read-modify-write instruction Note: Not used to addresses having different functions for reading and writing operations.
76
MB90210 Series
Table 2 Item A Description of Symbols in Instruction Table Description 32-bit accumlator The bit length is dependent on the instructions to be used. Byte : Lower 8-bit of AL Word :16-bit of AL Long : AL: 32-bit of AH Upper 16-bit of A Lower 16-bit of A Stack pointer (USP or SSP) Program counter Stack pointer upper limited register Stack pointer lower limited register Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB DTB, ADB, SSB, USB, DPR R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Specify shortened direct address. Specify direct address. Specify physical direct address. bit0 to bit15 of addr24 bit16 to bit 23 of addr24 I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data calculated by sign-extending an 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset value Vector number (0 to 15) Vector number (0 to 255) Bit address Specify PC relative branch. Specify effective address (code 00 to 07). Specify effective address (code 08 to 1F). Register allocation 77
AH AL SP PC SPCU SPCL PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 io #imm4 #imm8 #imm16 #imm32 ext (imm8) disp8 disp16 bp vct4 vct8 ( )b rel ear eam rlst
MB90210 Series
Table 3 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 Symbol RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 @RW0 @RW1 @RW2 @RW3 @RW0 + @RW1 + @RW2 + @RW3 + @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Field Address type Register direct "ea" corresponds to byte, word, and long word from left respectively. -- Number of bytes in address extension block*
Register indirect 0 Register indirect with post increment 0 Register indirect with 8-bit displacement 1
Register indirect with 16-bit displacement
2 0 0 2 2
Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address
Note: Number of bytes for address extension corresponds to "+" in the # (number of bytes) part in the instruction table.
78
MB90210 Series
Table 4 Code Number of Execution Cycles in Addressing Modes Operand Ri RWi RLi @RWj @RWj + @RWi + disp8 @RWj + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 (a)* Number of execution cycles for addressing modes Listed in instruction table 1 4 1 1 2 2 2 1
00 to 07 08 to 0B 0C to 0F 10 to 17 18 to 1B 1C 1D 1E 1F
Note: (a) is used for ~ (number of cycles) and B (correction value) in instruction table.
Table 5
Correction Value for Number of Cycles for Calculating Actual Number of Cycles Operand (b)* byte +0 +0 +0 +1 +1 +1 (c)* word +0 +0 +1 +1 +3 +3 (d)* long +0 +0 +2 +2 +6 +6
Internal register Internal RAM even address Internal RAM odd address Other than internal RAM even address Other than internal RAM odd address External data bus 8-bit
Notes: (b), (c), (d) is used for ~ (number of cycles) and B (correction value) in instruction table.
79
MB90210 Series
Table 6 Mnemonic MOV A, dir MOV A, addr16 MOV A, Ri MOV A, ear MOV A, eam MOV A, io MOV A, #imm8 MOV A, @A MOV A, @RLi + disp8 MOV A, @SP + disp8 MOVP A, addr24 MOVP A, @A MOVN A, #imm4 MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RWi + disp8 A, @RLi + disp8 A, @SP + disp8 MOVPX A, addr24 MOVPX A, @A dir, A addr16, A Ri, A ear, A eam, A io, A @RLi + disp8, A @SP + disp8, A addr24, A Ri, ear Ri, eam @A, Ri ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH A, ear A, eam Ri, ear Ri, eam Transmission Instruction (Byte) [50 Instructions] B (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) (b) (b) (b) 0 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 (b) 0 (b) (b) 0 (b) (b) Operation byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) (addr24) byte (A) ((A)) byte (A) imm4
LH AH
# ~ 2 2 2 3 1 1 1 2 2 + 2 + (a) 2 2 2 2 2 2 6 3 3 3 3 5 2 2 1 1 2 2 2 3 1 2 1 2 2 + 2 + (a) 2 2 2 2 2 2 3 2 6 3 3 3 3 5 2 2 2 2 2 3 1 1 2 2 2 + 2 + (a) 2 2 6 3 3 3 3 5 2 2 2 + 3 + (a) 3 2 3 2 2 + 3 + (a) 2 2 3 3 3 3 2 3 3 + 2 + (a) 2 2
byte (A) ((RLi) + disp8) byte (A) ((SP) + disp8)
Z Z Z Z Z Z Z Z Z Z Z Z Z
* * * * * * * - * * * - * * * * * * * * - * * * * - - - - - - - - - - - - - - - - - - - - - - - - -
I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
N * * * * * * * * * * * * R * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - -
Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - -
V - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
X X X X X X X X byte (A) ((RWi) + disp8) X byte (A) ((RLi) + disp8) X byte (A) ((SP) + disp8) X X byte (A) (addr24) X byte (A) ((A)) byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) - - - - - - - - - - - - - - - - - - - - Z Z - -
byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A))
MOV MOV MOV MOV MOV MOV MOV MOV MOVP MOV MOV MOVP MOV MOV MOV MOV MOV MOV MOV MOV XCH XCH XCH XCH
byte ((RLi) + disp8) (A) byte ((SP) + disp8) (A)
byte (addr24) (A) byte (Ri) (ear) byte (Ri) (eam) byte ((A)) (Ri) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 byte ((A)) (AH) byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam)
0 3 2 2 + 3 + (a) 2 x (b) 0 4 2 2 + 5 + (a) 2 x (b)
Note: For (a) and (b), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles."
80
MB90210 Series
Table 7 Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW # Transmission Instruction (Word) [40 Instructions] ~ B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) (c) (c) (c) 0 0 0 0 (c) (c) (c) (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) Operation word (A) (dir) word (A) (addr16) word (A) (SP) word (A) (RWi) word (A) (ear) word (A) (eam) word (A) (io) word (A) ((A)) word (A) imm16
LH AH
I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
N * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - -
Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - -
V - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 2 A, dir 2 3 A, addr16 2 1 A, SP 1 1 A, RWi 1 2 A, ear 2 + 2 + (a) A, eam 2 2 A, io 2 2 A, @A 2 3 A, #imm16 3 A, @RWi + disp8 2 6 3 A, @RLi + disp8 3 A, @SP + disp8 3 3 5 MOVPW A, addr24 2 2 MOVPW A, @A MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW
MOVPW MOVPW
- - - - - - - - - word (A) ((RWi) +disp8) - word (A) ((RLi) +disp8) - word (A) ((SP) + disp8) - - word (A) (addr24) - word (A) ((A))
* * * * * * * - * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW
dir, A addr16, A SP, #imm16 SP, A RWi, A ear, A eam, A io, A @RWi + disp8, A @RLi + disp8, A @SP + disp8, A addr24, A @A, RWi RWi, ear RWi, eam ear, RWi eam, RWi RWi, #imm16 io, #imm16 ear, #imm16 eam, #imm16
2 3 4 1 1 2 2+ 2 2 3 3 5 2 2 2+ 2 2+ 3 4 4 4+ 2
2 2 2 2 1 2 2 + (a) 2 3 6 3 3 3 2 3 + (a) 3 3 + (a) 2 3 2 2 + (a) 2
word (dir) (A) word (addr16) (A) word (SP) imm16 word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A)
- - - - - - - - word ((RWi) +disp8) (A) - word ((RLi) +disp8) (A) - word ((SP) + disp8) (A) - - word (addr24) (A) - word ((A)) (RWi) - word (RWi) (ear) - word (RWi) (eam) - word (ear) (RWi) - word (eam) (RWi) - word (RWi) imm16 - word (io) imm16 - word (ear) imm16 - word (eam) imm16 word ((A)) (AH) word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam) - - - - -
MOVW @AL, AH XCHW XCHW XCHW XCHW A, ear A, eam RWi, ear RWi, eam
0 3 2 2 + 3 + (a) 2 x (c) 0 4 2 2 + 5 + (a) 2 x (c)
Note: For (a) and (c), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles."
81
MB90210 Series
Table 8 Mnemonic MOVL A, ear MOVL A, eam MOVL A, #imm32 MOVL A, @SP + disp8 MOVPL A, addr24 MOVPL A, @A MOVPL @A, RLi MOVL MOVPL MOVL MOVL @SP + disp8, A addr24, A ear, A eam, A Transmission Instruction (Long) [11 Instructions] B 0 (d) 0 (d) (d) (d) (d) (d) (d) 0 (d) Operation long (A) (ear) long (A) (eam) long (A) imm32
long (A) ((SP) + disp8)
LH AH
# ~ 2 2 2 + 3 + (a) 5 3 3 4 5 4 2 3 2 5
long (A) (addr24) long (A) ((A)) long ((A)) (RLi)
long ((SP) + disp8) (A)
- - - - - - - - - - -
- - - - - - - - - - -
I - - - - - - - - - - -
S - - - - - - - - - - -
T - - - - - - - - - - -
N * * * * * * * * * * *
Z * * * * * * * * * * *
V - - - - - - - - - - -
C RMW - - - - - - - - - - - - - - - - - - - - - -
3 4 5 4 2 2 2 + 3 + (a)
long (addr24) (A) long (ear) (A) long (eam) (A)
Note: For (a) and (c), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles."
82
MB90210 Series
Table 9 Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A # 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ ~ Add/Subtract (Byte, Word, Long) [42 Instructions] B Operation byte (A) (A) +imm8 byte (A) (A) +(dir) byte (A) (A) +(ear) byte (A) (A) +(eam) byte (ear) (ear) + (A) byte (eam) (eam) + (A) byte (A) (AH) + (AL) + (C) byte (A) (A) + (ear) + (C) byte (A) (A) + (eam) + (C) byte (A) (A) - imm8 byte (A) (A) - (dir) byte (A) (A) - (ear) byte (A) (A) - (eam) byte (ear) (ear) - (A) byte (eam) (eam) - (A) byte (A) (AH) - (AL) - (C) byte (A) (A) - (ear) - (C) byte (A) (A) - (eam) - (C)
LH AH
I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
N * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
V * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
C RMW * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - * * - - - - - - - - * * - - - - - - - - * * - - - - - - * * - - - - - - - -
0 2 (b) 3 0 2 3 + (a) (b) 0 2 3 + (a) 2 x (b) 0 2 0 2 3 + (a) (b) 0 3 0 2 (b) 3 0 2 3 + (a) (b) 0 2 3 + (a) 2 x (b) 0 2 0 2 3 + (a) (b) 0 3 0 2 0 2 3 + (a) (c) 0 2 0 2 3 + (a) 2 x (c) 0 2 3 + (a) (c) 0 2 0 2 3 + (a) (c) 0 2 0 2 3 + (a) 2 x (c) 0 2 3 + (a) (c) 0 (d) 0 0 (d) 0
byte (A) (AH) + (AL) + (C) (decimal)
byte (A) (AH) - (AL) - (C) (decimal)
Z Z Z Z - Z Z Z Z Z Z Z Z Z - - Z Z Z Z - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ADDW A ADDW A, ear ADDW A, eam ADDW A, #imm16 ADDW ear, A ADDW eam, A ADDCW A, ear ADDCW A, eam SUBW A SUBW A, ear SUBW A, eam SUBW A, #imm16 SUBW ear, A SUBW eam, A SUBCW A, ear SUBCW A, eam ADDL ADDL ADDL SUBL SUBL SUBL A, ear A, eam
A, #imm32
word (A) (AH) + (AL) word (A) (A) + (ear) word (A) (A) + (eam) word (A) (A) + imm16 word (ear) - (ear) + (A) word (eam) - (eam) + (A) word (A) (A) + (ear) + (C) word (A) (A) + (eam) + (C) word (A) (AH) - (AL) word (A) (A) - (ear) word (A) (A) - (eam) word (A) (A) - imm16 word (ear) (ear) - (A) word (eam) (eam) - (A) word (A) (A) - (ear) - (C) word (A) (A) - (eam) - (C) long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) + imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) - imm32
A, ear A, eam
A, #imm32
5 2 2 + 6 + (a) 4 5 5 2 2 + 6 + (a) 4 5
Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles."
83
MB90210 Series
Table 10 Mnemonic INC INC DEC DEC INCW INCW ear eam ear eam ear eam # Increment/Decrement (Byte, Word, Long) [12 Instructions] ~ B Operation
LH AH
I - - - - - - - - - - - -
S - - - - - - - - - - - -
T - - - - - - - - - - - -
N * * * * * * * * * * * *
Z * * * * * * * * * * * *
V * * * * * * * * * * * *
C RMW - - - - - - - - - - - - * * * * * * * * - * * *
2 2 0 byte (ear) (ear) +1 2 + 3 + (a) 2 x (b) byte (eam) (eam) +1 2 2 0 byte (ear) (ear) -1 2 + 3 + (a) 2 x (b) byte (eam) (eam) -1 word (ear) (ear) +1 0 2 2 2 + 3 + (a) 2 x (c) word (eam) (eam) +1 2 2 0 word (ear) (ear) -1
- - - - - - - - - - - -
- - - - - - - - - - - -
DECW ear DECW eam INCL INCL DECL DECL ear eam ear eam
2 + 3 + (a) 2 x (c) word (eam) (eam) -1 long (ear) (ear) +1 0 4 2 2 + 5 + (a) 2 x (d) long (eam) (eam) +1 long (ear) (ear) -1 0 4 2 2 + 5 + (a) 2 x (d) long (eam) (eam) -1
Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles."
Table 11 Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW CMPL CMPL CMPL A A, ear A, eam A, #imm8 A A, ear A, eam A, #imm16 A, ear A, eam A, #imm32 # ~
Compare (Byte, Word, Long) [11 Instructions] B 0 0 (b) 0 0 0 (c) 0 0 (d) 0 Operation byte (AH) - (AL) byte (A) - (ear) byte (A) - (eam) byte (A) - imm8 word (AH) - (AL) word (A) - (ear) word (A) - (eam) word (A) - imm16 word (A) - (ear) word (A) - (eam) word (A) - imm32
LH AH
I - - - - - - - - - - -
S - - - - - - - - - - -
T - - - - - - - - - - -
N * * * * * * * * * * *
Z * * * * * * * * * * *
V * * * * * * * * * * *
C RMW * * * * * * * * * * * - - - - - - - - - - -
1 1 2 2 2 + 3 + (a) 2 2 1 1 2 2 2 + 3 + (a) 2 3 2 6 2 + 7 + (a) 5 3
- - - - - - - - - - -
- - - - - - - - - - -
Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles."
84
MB90210 Series
Table 12 Mnemonic DIVU DIVU DIVU DIVUW DIVUW A A, ear A, eam A, ear A, eam # 1 2 ~ *1 *2 Unsigned Multiply/Division (Word, Long) [11 Instructions] B 0 Operation
LH AH
I - - - - -
S - - - - -
T - - - - -
N - - - - -
Z - - - - -
V * * * * *
C RMW * * * * * - - - - -
2 + *3 2 2+ *4 *5
word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam) Quotient word (A) Remainder word (eam)
- - - - -
- - - - -
MULU MULU MULU MULUW MULUW MULUW
A A, ear A, eam A A, ear A, eam
1 2 2+ 1 2 2+
*8 0 byte (AH) byte (AL) word (A) *9 0 byte (A) byte (ear) word (A) *10 (b) byte (A) byte (eam) word (A) *11 0 word (AH) word (AL) long (A) *12 0 word (A) word (ear) long (A) *13 (c) word (A) word (eam) long (A)
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
Note: For (b) and (c), refer to "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." *1: Set to 3 when the division-by-0, 6 for an overflow, and 14 for normal operation. *2: Set to 3 when the division-by-0, 6 for an overflow, and 13 for normal operation. *3: Set to 5 + (a) when the division-by-0, 7 + (a) for an overflow, and 17 + (a) for normal operation. *4: Set to 3 when the division-by-0, 5 for an overflow, and 21 for normal operation. *5: Set to 4 + (a) when the division-by-0, 7 + (a) for an overflow, and 25 + (a) for normal operation. *6: When the division-by-0, (b) for an overflow, and 2 x (b) for normal operation. *7: When the division-by-0, (c) for an overflow, and 2 x (c) for normal operation. *8: Set to 3 when byte (AH) is zero, 7 when byte (AH) is not zero. *9: Set to 3 when byte (ear) is zero, 7 when byte (ear) is not zero. *10:Set to 4 + (a) when byte (eam) is zero, 8 + (a) when byte (eam) is not zero. *11:Set to 3 when word (AH) is zero, 11 when word (AH) is not zero. *12:Set to 4 when word (ear) is zero, 11 when word (ear) is not zero. *13:Set to 4 + (a) when word (eam) is zero, 12 + (a) when word (eam) is not zero.
85
MB90210 Series
Table 13 Mnemonic DIV A # 2 Signed multiplication/division (Word, Long) [11 Instructions] ~ *1 B Operation 0 word (AH)/byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam) Quotient word (A) Remainder word (eam) 0 byte (AH) x byte (AL) word (A) 0 byte (A) x byte (ear) word (A) (b) byte (A) x byte (eam) word (A) 0 word (AH) x word (AL) long (A) 0 word (A) x word (ear) long (A) (b) word (A) x word (eam) long (A)
LH AH
Z
-
I -
S -
T -
N -
Z -
V *
C RMW * -
DIV
A, ear
2
*2
Z
-
-
-
-
-
-
*
*
-
DIV
A, eam
2 + *3
Z
-
-
-
-
-
-
*
*
-
DIVW
A, ear
2
*4
-
-
-
-
-
-
-
*
*
-
DIVW
A, eam
2 + *5
-
-
-
-
-
-
-
*
*
-
MUL MUL MUL MULW MULW MULW
A A, ear A, eam A A, ear A, eam
2 2 2+ 2 2 2+
*8 *9 *10 *11 *12 *13
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
For (b) and (c), refer to "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." Set to 3 for divide-by-0, 8 or 18 for an overflow, and 18 for normal operation. Set to 3 for divide-by-0, 10 or 21 for an overflow, and 22 for normal operation. Set to 4 + (a) for divide-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation. Positive divided: Set to 4 for divide-by-0, 10 or 29 for an overflow, and 30 for normal operation. Negative divided: Set to 4 for divide-by-0, 11 or 30 for an overflow, and 31 for normal operation. *5: Positive divided: Set to 4 + (a) for divide-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation. Negative divided: Set to 4 + (a) for divide-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal operation. *6: Set to (b) when the division-by-0 or an overflow, and 2 x (b) for normal operation. *7: Set to (c) when the division-by-0 or an overflow, and 2 x (c) for normal operation. *8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10:Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11:Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *12:Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13:Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. Note: When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two values because of detection before and after an operation. When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed. *1: *2: *3: *4:
86
MB90210 Series
Table 14 Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW NOTW NOTW NOTW A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A ear eam A A, #imm16 A, ear A, eam ear, A eam, A A A, #imm16 A, ear A, eam ear, A eam, A A A, #imm16 A, ear A, eam ear, A eam, A A ear eam # ~ B Logic 1 (Byte, Word) [39 Instructions] Operation byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A) byte (A) not (A) byte (ear) not (ear) byte (eam) not (eam) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A) word (A) not (A) word (ear) not (ear) word (eam) not (eam)
LH AH
I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
N * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
V R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * - - - * * - - - * * - * * - - - - * * - - - - * * - - - - * * - * *
0 2 2 0 2 2 2 + 3 + (a) (b) 0 3 2 2 + 3 + (a) 2 x (b) 0 2 2 0 2 2 2 + 3 + (a) (b) 0 3 2 2 + 3 + (a) 2 x (b) 0 2 2 0 2 2 2 + 3 + (a) (b) 0 3 2 2 + 3 + (a) 2 x (b) 0 2 1 0 2 2 2 + 3 + (a) 2 x (b) 0 2 1 0 2 3 0 2 2 2 + 3 + (a) (c) 0 3 2 2 + 3 + (a) 2 x (c) 0 2 1 0 2 3 0 2 2 2 + 3 + (a) (c) 0 3 2 2 + 3 + (a) 2 x (c) 0 2 1 0 2 3 0 2 2 2 + 3 + (a) (c) 0 3 2 2 + 3 + (a) 2 x (c) 0 2 1 0 3 2 2 + 3 + (a) 2 x (c)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Note: For (a) to (c), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles."
87
MB90210 Series
Table 15 Mnemonic ANDL ANDL ORL ORL XORL XORL A, ear A, eam A, ear A, eam A, ear A, eam # ~ B 0 (d) 0 (d) 0 (d) Logic 2 (Long) [6 Instructions] Operation long (A) (A) and (ear) long (A) (A) and (eam) long (A) (A) or (ear) long (A) (A) or (eam) long (A) (A) xor (ear) long (A) (A) xor (eam)
LH AH
I - - - - - -
S - - - - - -
T - - - - - -
N * * * * * *
Z * * * * * *
V R R R R R R
C RMW - - - - - - - - - - - -
2 5 2 + 6 + (a) 2 5 2 + 6 + (a) 2 5 2 + 6 + (a)
- - - - - -
- - - - - -
Note: For (a) and (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles."
Table 16 Mnemonic NEG NEG NEG A ear eam # 1 ~ 2
RG
Sign Reverse (Byte, Word) [6 Instructions] B 0 Operation byte (A) 0 - (A)
LH AH
I - - - - - -
S - - - - - -
T - - - - - -
N * * * * * *
Z * * * * * *
V * * * * * *
C * * * * * *
RMW
0
X - - - - -
- - - - - -
- - * - - *
byte (ear) 0 - (ear) 0 2 3 2 2 + 5 + (a) 0 2 x (b) byte (eam) 0 - (eam) 1 2 0 0 word (A) 0 - (A)
NEGW A NEGW ear NEGW eam
2 3 2 2 + 5 + (a) 0
word (ear) 0 - (ear) 0 2 x (c) word (eam) 0 - (eam)
Note: For (a) and (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles."
Table 17 Mnemonic ABS A ABSW A ABSL A # 2 2 2 ~ 2 2 4
Absolute Values (Byte, Word, Long) [3 Instructions] B 0 0 0 Operation byte (A) Absolute value (A) word (A) Absolute value (A) long (A) Absolute value (A)
LH AH
I - - -
S - - -
T - - -
N * * *
Z * * *
V * * *
C RMW - - - - - -
Z - -
- - -
Table 18 Mnemonic NRML A, R0 # 2 ~ *1 RG 1
Normalize Instruction (Long) [1 Instruction] B 0 Operation long (A) Shift to where "1" is originally located byte (R0) Number of shifts in the operation
LH AH
I -
S -
T -
N -
Z *
V -
C -
RMW
-
-
-
* : Set to 5 when the accumulator is all "0", otherwise set to 5 + (R0).
88
MB90210 Series
Table 19 Mnemonic RORC A ROLC A RORC RORC ROLC ROLC ASR LSR LSL ASR LSR LSL ear eam ear eam A, R0 A, R0 A, R0
A, #imm8 A, #imm8 A, #imm8
Shift Type Instruction (Byte, Word, Long) [27 Instructions] B 0 0 Operation byte (A) With right-rotate carry byte (A) With left-rotate carry byte (ear) With right-rotate carry byte (eam) With right-rotate carry byte (ear) With left-rotate carry byte (eam) With left-rotate carry
byte (A) Arithmetic right barrel shift (A, R0) byte (A) Logical right barrel shift (A, R0) byte (A) Logical left barrel shift (A, R0)
byte (A) Arithmetic right barrel shift (A, imm8)
# 2 2 2 2+ 2 2+ 2 2 2 3 3 3
~ 2 2 2
3 + (a)
LH AH
I - - - - - - - - - - - - - - - - - - - - - - - - - - -
STNZVC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * - * * - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * *
RMW
- - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - -
- - * * * * - - - - - - - - - - - - - - - - - - - - -
2
3 + (a)
0 2 x (b) 0 2 x (b) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
*1 *1 *1 *3 *3 *3 2 2 2 *1 *1 *1 *3 *3 *3 *2 *2 *2 *4 *4 *4
byte (A) Logical right barrel shift (A, imm8) byte (A) Logical left barrel shift (A, imm8) word (A) Arithmetic right shift (A, 1 bit) word (A) Logical right shift (A, 1 bit) word (A) Logical left shift (A, 1 bit) word (A) Arithmetic right barrel shift (A, R0) word (A) Logical right barrel shift (A, R0) word (A) Logical left barrel shift (A, R0)
word (A) Arithmetic right barrel shift (A, imm8)
ASRW A 1 LSRW A/SHRW A 1 LSLW A/SHLW A 1 ASRW A, R0 LSRW A, R0 LSLW A, R0 2 2 2
** *R -* * * - * * - * * - * * - * * * * * * * * * * * *
ASRW A, #imm8 3 LSRW A, #imm8 3 LSLW A, #imm8 3 ASRL A, R0 LSRL A, R0 LSLL A, R0 2 2 2
word (A) Logical right barrel shift (A, imm8) word (A) Logical left barrel shift (A, imm8) long (A) Arithmetic right barrel shift (A, R0) long (A) Logical right barrel shift (A, R0) long (A) Logical left barrel shift (A, R0)
long (A) Arithmetic right barrel shift (A, imm8)
ASRL A, #imm8 3 LSRL A, #imm8 3 LSLL A, #imm8 3
long (A) Logical right barrel shift (A, imm8) long (A) Logical left barrel shift (A, imm8)
Note: For (a) and (b), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." *1: *2: *3: *4: Set to 3 when R0 is 0, otherwise 3 + (R0). Set to 3 when R0 is 0, otherwise 4 + (R0). Set to 3 when imm8 is 0, otherwise 3 + imm8. Set to 3 when imm8 is 0, otherwise 4 + imm8.
89
MB90210 Series
Table 20 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP CALLP CALLP
@A
Branch 1 [31 Instructions] Operation
LH AH
# 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
~ *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1
B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0
I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
S T N Z V C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Branch if (Z) = 1 Branch if (Z) = 0 Branch if (C) = 1 Branch if (C) = 0 Branch if (N) = 1 Branch if (N) = 0 Branch if (V) = 1 Branch if (V) = 0 Branch if (T) = 1 Branch if (T) = 0 Branch if (V) xor (N) = 1 Branch if (V) xor (N) = 0
Branch if ((V) xor (N)) or (Z) = 1 Branch if ((V) xor (N)) or (Z) = 0
Branch if (C) or (Z) = 1 Branch if (C) or (Z) = 0 Branch unconditionally word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
addr16 @ear @eam @ear *3 @eam *3 addr24 @ear *4 @eam *4 addr16 *5 #vct4 *5 @ear *6 @eam *6 addr24 *7
2 1 2 3 3 2 2 + 4 + (a) 3 2 2 + 4 + (a) 3 4
(c) 4 2 2 + 5 + (a) 2 x (c) (c) 5 3 2 x (c) 5 1 2 x (c) 7 2 2 + 8 + (a) 4 7 *2 2 x (c)
word (PC) ad24 0 - 15, (PCB) ad24 16 - 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call instruction word (PC) (ear) 0 - 15 (PCB) (ear) 16 - 23 word (PC) (eam) 0 - 15 (PCB) (eam) 16 - 23 word (PC) addr0 - 15, (PCB) addr16 - 23
word (PC) (ear), (PCB) (ear + 2) word (PC) (eam), (PCB) (eam + 2)
Note: For (a), (c) and (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." *1: *2: *3: *4: *5: *6: *7: Set to 3 when branch is executed, and 2 when branch is not executed. 3 x (c) + (b) Reads (word) of the branch destination address. W pushes to stack (word), and R reads (word) of the branch destination address. Pushes to stack (word). W pushes to stack (long), and R reads (long) of the branch destination address. Pushes to stack (long).
90
MB90210 Series
Table 21 Mnemonic CBNE A, #imm8, rel CWBNE A, #imm16, rel CBNE CBNE CWBNE CWBNE DBNZ DBNZ ear, #imm8, rel eam, #imm8, rel ear, #imm16, rel eam, #imm16, rel ear, rel eam, rel # ~ B 0 0 0 (b) 0 (c) 0 Branch 2 [20 Instructions] Operation
Branch if word (A) imm16
LH AH
I - - - - - - - - - - R R R R * * -
S - - - - - - - - - - S S S S * * -
T - - - - - - - - - - - - - - * * -
N * * * * * * * * * * - - - - * * -
Z * * * * * * * * * * - - - - * * -
V * * * * * * * * * * - - - - * * -
C RMW * * * * * * - - - - - - - - * * - - - - - - - - * - * - - - - - - -
3 *1 4 *1 4 4+ 5 5+ *1 *3 *1 *3
Branch if byte (A) imm8
- - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - -
Branch if byte (ear) imm8 Branch if byte (eam) imm8 Branch if word (ear) imm16 Branch if word (eam) imm16
byte (ear) = (ear) - 1, Branch if (ear) 0 3 + *4 2 x (b) byte (eam) = (eam) - 1, Branch if (eam) 0 word (ear) = (ear) - 1, Branch if (ear) 0 3 + *4 2 x (c) word (eam) = (eam) - 1, Branch if (eam) 0 3 *2 0 2 3 4 1 1 2 2 14 12 13 14 9 11 6 8 x (c) 6 x (c) 6 x (c) 8 x (c) 6 x (c) *5 (c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt Return from interrupt Stores old frame pointer in the beginning of the function, set new frame pointer, and reserves local pointer area Restore old frame pointer from stack in the end of the function Return from subroutine Return from subroutine
3 *2
DWBNZ ear, rel DWBNZ eam, rel INT #vct8 INT addr16 INTP addr24 INT9 RETI RETIQ *6 LINK #imm8
UNLINK
1
5
(c)
-
-
-
-
-
-
-
-
-
-
RET *7 RETP *8
1 1
4 5
(c) (d)
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." *1: *2: *3: *4: *5: *6: Set to 4 when branch is executed, and 3 when branch is not executed. Set to 5 when branch is executed, and 4 when branch is not executed. Set to 5 + (a) when branch is executed, and 4 + (a) when branch is not executed. Set to 6 + (a) when branch is executed, and 5 + (a) when branch is not executed. Set to 3 x (b) + 2 x (c) when an interrupt request is issued, and 6 x (c) for return. This is a high-speed interrupt return instruction. In the instruction, an interrupt request is detected. When an interrupt occurs, stack operation is not performed, with this instruction branching to the interrupt vector. *7: Return from stack (word). *8: Return from stack (long).
91
MB90210 Series
Table 22 Mnemonic PUSHW PUSHW PUSHW PUSHW POPW POPW POPW POPW JCTX AND OR
MOV MOV
Miscellaneous Control Types (Byte, Word, Long) [36 Instructions] ~ 3 3 3 *3 3 3 3 *2 9 3 3 2 2 B (c) (c) (c) *4 (c) (c) (c) *4 Operation
LH AH
# 1 1 1 2 1 1 1 2 1 2 2 2 2
I - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - -
S T N Z V C RMW - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - * * * - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - * * * - - - - - - - - - - - * * * - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
A AH PS rlst A AH PS rlst @A
CCR, #imm8 CCR, #imm8
word (SP) (SP) - 2, ((SP)) (A) - word (SP) (SP) - 2, ((SP)) (AH) - word (SP) (SP) - 2, ((SP)) (PS) - (PS) (PS) - 2n, ((SP)) (rlst) -
word (A) ((SP)), (SP) (SP) + 2 word (AH) ((SP)), (SP) (SP) + 2 word (PS) ((SP)), (SP) (SP) + 2 (rlst) ((SP)), (SP) (SP) + 2n
- - - - * - - - - - - - - - - * * - - * - - - - - - - - - - - - - - - -
- - - - -
6 x (c) Context switch instruction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
byte (CCR) (CCR) and imm8 - - byte (CCR) (CCR) or imm8 byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word(A) ear word (A) eam - - - - - -
RP #imm8 , ILM, #imm8
MOVEA MOVEA MOVEA MOVEA
RWi, ear RWi, eam A, ear A, eam
3 2 2 + 2 + (a) 2 2 2 + 1 + (a) 2 3 3 3 *1 1 2 1 1 1 1 1 1 1 2 2 2 2 *5 *6 *7
ADDSP #imm8 ADDSP #imm16 MOV MOV MOV NOP ADB DTB PCB SPB NCC CMR
MOVW SPCU, #imm16 MOVW SPCL, #imm16
word (SP) (SP) + ext (imm8) - - word (SP) (SP) + imm16 byte (A) (brgl) byte (brg2) (A) byte (brg2) imm8 No operation
Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space Prefix code for no change in flag Prefix for common register bank
A, brgl 2 brg2, A 2 brg2, #imm8 3 1 1 1 1 1 1 1 4 4 2 2 2 2 2
Z - - - - - - - - - - - - - Z Z Z
SETSPC CLRSPC BTSCN A BTSCNS A BTSCND A
word (SPCU) (imm16) word (SPCL) (imm16) Enables stack check operation. Disables stack check operation.
Bit position of 1 in byte (A) from word (A)
Bit position (x 2) of 1 in byte (A) from word (A) Bit position (x 4) of 1 in byte (A) from word (A)
Note: For (a) and (c), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." *1: PCB, ADB, SSB, USB, and SPB : 1 state DTB : 2 states DPR : 3 states *2: 3 + 4 x (number of POPs) *3: 3 + 4 x (number of PUSHes) *4: (Number of POPs) x (c), or (number of PUSHes) x (c) *5: Set to 3 when AL is 0, 5 when AL is not 0. *6: Set to 4 when AL is 0, 6 when AL is not 0. *7: Set to 5 when AL is 0, 7 when AL is not 0. 92
MB90210 Series
Table 23 Mnemonic MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A SETB dir:bp SETB addr16:bp SETB io:bp CLRB dir:bp CLRB addr16:bp CLRB io:bp BBC BBC BBC BBS BBS BBS SBBS dir:bp, rel addr16:bp, rel io:bp, rel dir:bp, rel addr16:bp, rel io:bp, rel addr16:bp, rel # 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 ~ 3 3 3 4 4 4 4 4 4 4 4 4 *1 *1 *1 *1 *1 *1 *2 *3 *3 Bit Manipulation Instruction [21 Instructions] B (b) (b) (b) Operation byte (A) (dir:bp) b byte (A) (addr16:bp) b byte (A) (io:bp) b
LH AH
I - - - - - - - - - - - - - - - - - - - - -
S T N Z V C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * - - - - - - - - - - - - - - - * * * * * * - - - - - - * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * - - - - - - * - -
Z Z Z - - - - - - - - - - - - - - - - - -
* * * - - - - - - - - - - - - - - - - - -
2 x (b) bit (dir:bp) b (A) 2 x (b) bit (addr16:bp) b (A) 2 x (b) bit (io:bp) b (A) 2 x (b) bit (dir:bp) b 1 2 x (b) bit (addr16:bp) b 1 2 x (b) bit (io:bp) b 1 2 x (b) bit (dir:bp) b 0 2 x (b) bit (addr16:bp) b 0 2 x (b) bit (io:bp) b 0 (b) (b) (b) (b) (b) (b) Branch if (dir:bp) b = 0 Branch if (addr16:bp) b = 0 Branch if (io:bp) b = 0 Branch if (dir:bp) b = 1 Branch if (addr16:bp) b = 1 Branch if (io:bp) b = 1
2 x (b) Branch if (addr16:bp) b = 1, bit = 1 *4 *4 Wait until (io:bp) b = 1 Wait until (io:bp) b = 0
WBTS io:bp WBTC io:bp
Note: For (b), refer to "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." *1: *2: *3: *4: Set to 5 when branch is executed, and 4 when branch is not executed. 7 if conditions are met, 6 when conditions are not met. Indeterminate times Until conditions are met
93
MB90210 Series
Table 24 Mnemonic SWAP SWAPW/XCHW AL, AH EXT EXTW ZEXT ZEXTW Accumulator Manipulation Instruction (Byte, Word) [6 Instructions] # 1 1 1 1 1 1 ~ 3 2 1 2 1 1 B 0 0 0 0 0 0 Operation byte (A) 0 - 7 (A) 8 - 15 word (AH) (AL) byte sign-extension word sign-extension byte zero-extension word zero-extension
LH AH
I - - - - - -
S - - - - - -
T - - - - - -
N - - * * R R
Z - - * * * *
V - - - - - -
C RMW - - - - - - - - - - - -
- - X - Z -
- * - X - Z
Table 25 Mnemonic MOVS/MOVSI MOVSD SCEQ/SCEQI SCEQD FISL/FILSI MOVSW/MOVSWI MOVSWD SCWEQ/SCWEQI SCWEQD FILSW/FILSWI # 2 2 2 2 ~ *2 *2 *1 *1 B
String Instruction [10 Instructions] Operation
LH AH
I - - - - - - - - - -
S - - - - - - - - - -
T - - - - - - - - - -
N - - * * * - - * * *
Z - - * * * - - * * *
V - - * * - - - * * -
C RMW - - * * - - - * * - - - - - - - - - - -
*3 byte transfer @AH + @AL +, Counter = RW0 *3 byte transfer @AH - @AL -, Counter = RW0 *4 byte search (@AH +) - AL, Counter = RW0 *4 byte search (@AH -) - AL, Counter = RW0
- - - - - - - - - -
- - - - - - - - - -
2 5m + 6 *5 byte fill @AH + AL, Counter = RW0 2 2 2 2 *2 *2 *1 *1 *6 word transfer @AH + @AL +, Counter = RW0 *6 word transfer @AH - @AL -, Counter = RW0 *7 word search (@AH +) - AL, Counter = RW0 *7 word search (@AH -) - AL, Counter = RW0
2 5m + 6 *8 word fill @AH + AL, Counter = RW0
m: RW0 value (counter value) *1: *2: *3: *4: *5: *6: *7: *8: 3 when RW0 is 0, 2 + 6 x (RW0) when count out, and 6n + 4 when matched 4 when RW0 is 0, otherwise 2 + 6 x (RW0) (b) x (RW0) (b) x n (b) x (RW0) (c) x (RW0) (c) x n (c) x (RW0)
94
MB90210 Series
Table 26 Mnemonic MOVM @A, @RLi, #imm8 MOVM @A, eam, #imm8 MOVM addr16, @RLi, #imm8 # 3 3+ 5 Multiple Data Transfer Instructions [18 Instruction] ~ *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 B Operation *3 Multiple data transfer byte ((A)) ((RLi)) *3 Multiple data transfer byte ((A)) (eam) *3 Multiple data transfer byte (addr16) ((RLi)) *3 Multiple data transfer byte (addr16) (eam) *4 Multiple data transfer word ((A)) ((RLi)) *4 Multiple data transfer word ((A)) (eam) *4 Multiple data transfer word (addr16) ((RLi)) *4 Multiple data transfer word (addr16) (eam) *3 Multiple data transfer byte ((RLi)) ((A)) *3 Multiple data transfer byte (eam) ((A)) *3 Multiple data transfer byte ((RLi)) (addr16) *3 Multiple data transfer byte (eam) (addr16) *4 Multiple data transfer word ((RLi)) ((A)) *4 Multiple data transfer word (eam) ((A)) *4 Multiple data transfer word ((RLi)) (addr16) *4 Multiple data transfer word (eam) (addr16) *3 Multiple data transfer byte (bnk: addr16) (bnk: addr16) *4 Multiple data transfer word (bnk: addr16) (bnk: addr16)
LH AH
- - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - -
I - - - - - - - - - - - - - - - - -
S - - - - - - - - - - - - - - - - -
T - - - - - - - - - - - - - - - - -
N - - - - - - - - - - - - - - - - -
Z - - - - - - - - - - - - - - - - -
V - - - - - - - - - - - - - - - - -
C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOVM addr16, @eam, #imm8 5 +
MOVMW@A, @RLi, #imm8 MOVMW@A, eam, #imm8 MOVMWaddr16, @RLi, #imm8
3 3+ 5
MOVMWaddr16, @eam, #imm8 5 +
MOVM @RLi, @A, #imm8 MOVM @eam, A, #imm8 MOVM @RLi, addr16, #imm8
3 3+ 5
MOVM @eam, addr16, #imm8 5 +
MOVMW@RLi, @A, #imm8 MOVMW@eam, A, #imm8 MOVMW@RLi, addr16, #imm8
3 3+ 5
MOVMW@eam, addr16, #imm8 5 +
MOVM bnk: addr16, bnk: addr16, #imm8*5
MOVMWbnk: addr16,
7
7
*1
-
-
-
-
-
-
-
-
-
-
bnk: addr16, #imm8*5
*1: *2: *3: *4: *5:
256 when 5 + imm8 x 5, imm8 is 0. 256 when 5 + imm8 x 5 + (a), imm8 is 0. (Number of transfer cycles) x (b) x 2 (Number of transfer cycles) x (c) x 2 The bank register specified by bnk is the same as that for the MOVS instruction.
95
MB90210 Series
s ORDERING INFORMATION
Part number MB90214 MB90P214A MB90P214B MB90W214A MB90W214B MB90V210 Type MB90214PF MB90P214PF MB90P214BPF MB90W214ZF MB90W214BZF MB90V210CR Package 80-pin Plastic QFP (FPT-80P-M06) 80-pin Ceramic QFP (FPT-80C-C02) 256-pin Ceramic PGA (PGA-256C-A02) Only ES level For evaluation Remarks
96
MB90210 Series
s PACKAGE DIMENSIONS
80-pin Plastic QFP (FPT-80P-M06)
23.900.40(.941.016)
64 65
20.000.20(.787.008)
41 40
3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF)
14.000.20 (.551.008)
INDEX
80 25
17.900.40 (.705.016)
12.00(.472) REF
16.300.40 (.642.016)
"A" LEAD No.
1 24
0.80(.0315)TYP
0.350.10 (.014.004)
0.16(.006)
M
0.150.05(.006.002)
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.40(.724)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.58(.023)MAX
Details of "B" part
0 10 0.800.20 (.031.008)
C
1994 FUJITSU LIMITED F80010S-3C-2
Dimensions in mm (inches)
80-pin Ceramic QFP (FPT-80C-C02)
0.05(.002)MIN (STAND OFF)
O8.89(.350)TYP
17.900.30 12.00(.472) (.705.012) REF +0.45 14.00 -0.15 +.018 .551-.006
16.300.25 (.642.010)
INDEX AREA 0.80(.0315)TYP 0.350.10 (.014.004) 18.40(.724) REF 20.00 -0.20 +.020 .787 -.008 23.900.30 (.941.012)
+0.50
0.150.05 (.006.002) 1.450.20 (.057.008) 3.30(.130)MAX
(Mounting height)
22.300.25 (.878.010)
0.800.20 (.0315.008)
C
1994 FUJITSU LIMITED F80018SC-1-2
Dimensions in mm (inches) 97
MB90210 Series
MEMO
98
MB90210 Series
MEMO
99
MB90210 Series
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9710 (c) FUJITSU LIMITED Printed in Japan
10

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